Alternatives and similar repositories for FPGA_Tutorial_with_HLS

Users that are interested in FPGA_Tutorial_with_HLS are comparing it to the libraries listed below

• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆75Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆121Updated 3 months ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆186Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆86Updated 2 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆112Updated 5 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆48Updated this week
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆98Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆101Updated 5 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆143Updated 7 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆205Updated 4 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆22Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆48Updated 6 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆68Updated 3 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆58Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆190Updated 2 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆106Updated 2 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆43Updated 3 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆33Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆144Updated 6 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆175Updated 2 years ago