hajin-kim / FPGA_Tutorial_with_HLSLinks
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
☆16Updated 4 years ago
Alternatives and similar repositories for FPGA_Tutorial_with_HLS
Users that are interested in FPGA_Tutorial_with_HLS are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆59Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- A 2D convolution hardware implementation written in Verilog☆50Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆80Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- Introductory course into static timing analysis (STA).☆98Updated 3 months ago
- ☆64Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- A collection of commonly asked RTL design interview questions☆35Updated 8 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆16Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆37Updated 6 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 9 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- SoC design & prototyping☆14Updated 4 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- BlackParrot on Zynq☆47Updated last week
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆40Updated 3 years ago
- Verilog/SystemVerilog Guide☆73Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year