Alternatives and similar repositories for RISC-V-Single-Cycle-Processor

Users that are interested in RISC-V-Single-Cycle-Processor are comparing it to the libraries listed below

• Ummidichandrika / 100-Days-of-RTL
  ☆113Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 10 months ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆83Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆50Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆25Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆132Updated last year
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆139Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆115Updated 11 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆62Updated 2 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆126Updated 7 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆105Updated 6 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆22Updated 4 years ago
• Artityagi123456789 / 15DaysofUVM
  ☆17Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆66Updated last year
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆31Updated 8 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆155Updated last year
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• Samaksh36 / Cadence_VLSI-Design-Flow
  RTL to GDS via Cadence Tools
  ☆12Updated 3 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆19Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆121Updated 7 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆27Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆63Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆18Updated 3 months ago