In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V Single Cycle.
☆23Aug 28, 2024Updated last year
Alternatives and similar repositories for RISC-V-Single-Cycle-Processor
Users that are interested in RISC-V-Single-Cycle-Processor are comparing it to the libraries listed below
Sorting:
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- Hardware and Software Co-design implementations☆15Dec 5, 2019Updated 6 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Sep 16, 2018Updated 7 years ago
- opensource EDA tool flor VLSI design☆36Sep 17, 2023Updated 2 years ago
- ☆35Nov 24, 2021Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- Convolutional Neural Network in C (for educational purposes)☆30Jan 18, 2021Updated 5 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated last year
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆10Feb 23, 2023Updated 3 years ago
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆17Apr 26, 2023Updated 2 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆13Sep 18, 2025Updated 5 months ago
- Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision☆12Jan 19, 2026Updated last month
- ☆11Dec 23, 2025Updated 2 months ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- “集合与图论”课程学习与复习资料☆14Nov 11, 2024Updated last year
- ☆16Mar 27, 2024Updated last year
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆22Sep 4, 2025Updated 6 months ago
- ☆14Sep 27, 2022Updated 3 years ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆16Feb 25, 2021Updated 5 years ago
- 单周期CPU设计与实现☆14Dec 30, 2022Updated 3 years ago
- A program that can losslessly compress and decompress files using Huffman Encoding☆15Dec 19, 2018Updated 7 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- 武汉大学计算机组成与设计课程单周期CPU处理器实现,使用RISC-V语言实现。☆10Mar 14, 2024Updated last year
- An inhouse RISC-V 32-bits CPU☆18Feb 12, 2026Updated 3 weeks ago
- A Single Cycle Risc-V 32 bit CPU☆68Jan 14, 2026Updated last month
- This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.☆22May 12, 2025Updated 9 months ago
- ☆13Jul 2, 2016Updated 9 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- ☆15Jul 30, 2021Updated 4 years ago
- 👻 Simple Undertale-like game on Basys3 FPGA written in Verilog☆16Jul 3, 2020Updated 5 years ago
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for …☆17Oct 24, 2017Updated 8 years ago
- A demo of running a custom object detection model on Raspberry Pi☆15Sep 14, 2022Updated 3 years ago
- ai_accelerator_basic_for_student (no solve)☆16Mar 27, 2020Updated 5 years ago
- Course material for Purdue ECE57000 Artificial Intelligence☆16Nov 8, 2018Updated 7 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Oct 5, 2023Updated 2 years ago
- Implementation of adaptive filters such as BMFLC, FLC, and WFLC in C++ using Arduino☆16Jul 13, 2017Updated 8 years ago