EkthaReddy / RISC-V-Single-Cycle-ProcessorLinks
In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V Single Cycle.
☆20Updated last year
Alternatives and similar repositories for RISC-V-Single-Cycle-Processor
Users that are interested in RISC-V-Single-Cycle-Processor are comparing it to the libraries listed below
Sorting:
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆59Updated last year
- ☆116Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆176Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- A collection of commonly asked RTL design interview questions☆38Updated 8 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆108Updated 2 years ago
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆74Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Updated last year
- Architectural design of data router in verilog☆32Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- ☆16Updated last year
- This repo provide an index of VLSI content creators and their materials☆165Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆16Updated 2 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆55Updated last year
- AXI DMA 32 / 64 bits☆124Updated 11 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆46Updated last year
- ☆17Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆42Updated 5 months ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆27Updated 2 years ago
- ☆17Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆181Updated last year
- UVM and System Verilog Manuals☆48Updated 7 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆22Updated 4 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆25Updated 7 months ago