Alternatives and similar repositories for RISC-V-Single-Cycle-Processor:

Users that are interested in RISC-V-Single-Cycle-Processor are comparing it to the libraries listed below

• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 7 months ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆16Updated 11 months ago
• Devipriya1921 / Traffic-Light-Controller-using-Verilog
  Verilog Project
  ☆10Updated 3 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆16Updated last week
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆42Updated 8 months ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 5 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆17Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆22Updated last year
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• abdelazeem201 / ICC2_scripts
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
  ☆16Updated last year
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆144Updated 9 months ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆16Updated 10 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆67Updated last year
• shubhi704 / APB-Protocol
  ☆41Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆23Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆49Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆82Updated 5 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆50Updated last year
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• Abhishek-Sharma182005 / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆11Updated 2 months ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆36Updated 2 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆29Updated 2 years ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated last year