☆35Nov 24, 2021Updated 4 years ago
Alternatives and similar repositories for 32-bit-RISC-V-Cpu-Core
Users that are interested in 32-bit-RISC-V-Cpu-Core are comparing it to the libraries listed below
Sorting:
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- Notes and Assignments of embedded systems study group☆83Jan 7, 2024Updated 2 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆25Aug 28, 2024Updated last year
- SRA's seminar on Introduction to Computer Vision Fundamentals☆150Mar 8, 2026Updated 2 weeks ago
- A line follower simulation created in CoppeliaSim, with a C++ interface for CoppeliaSim's Remote API☆23Jul 3, 2022Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆111Jul 9, 2023Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆36Apr 13, 2024Updated last year
- Convolutional Neural Network in C (for educational purposes)☆30Jan 18, 2021Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- risc-v single cycle implementation☆20Jun 7, 2021Updated 4 years ago
- Single Cycle 32 bit MIPS☆20Dec 24, 2022Updated 3 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago
- ☆41Apr 2, 2018Updated 7 years ago
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆26Aug 28, 2016Updated 9 years ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆17Feb 25, 2021Updated 5 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Basic Web Chatting platform in Flask☆11Mar 20, 2021Updated 5 years ago
- ☆13May 8, 2025Updated 10 months ago
- A 10bit SAR ADC in Sky130☆33Dec 4, 2022Updated 3 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆11Nov 23, 2020Updated 5 years ago
- Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆136Mar 2, 2026Updated 2 weeks ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 3 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- OAuth 2.0 Library - WE ARE NO LONGER MAINTAINING THIS LIBRARY, PLEASE SEE this fork: https://github.com/NateFerrero/pyoauth2☆117Sep 3, 2021Updated 4 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- A Chip-8 disassembler developed using recursive traversal algorithm.☆10Oct 2, 2018Updated 7 years ago
- A word processor built with HTML, CSS, and JavaScript☆22Sep 30, 2018Updated 7 years ago
- Implementation of adaptive filters such as BMFLC, FLC, and WFLC in C++ using Arduino☆16Jul 13, 2017Updated 8 years ago
- RISC-V Summit China 2023☆40Sep 27, 2023Updated 2 years ago
- MOVED TO https://github.com/jezdez/django-avatar☆15Oct 8, 2012Updated 13 years ago
- A demo of running a custom object detection model on Raspberry Pi☆15Sep 14, 2022Updated 3 years ago
- ☆18Nov 11, 2025Updated 4 months ago
- アルゴリズムのgolang、python実装☆11Mar 4, 2019Updated 7 years ago
- ☆18Jul 12, 2024Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year