siddharth23-8 / 32-bit-RISC-V-Cpu-Core
☆32Updated 3 years ago
Alternatives and similar repositories for 32-bit-RISC-V-Cpu-Core:
Users that are interested in 32-bit-RISC-V-Cpu-Core are comparing it to the libraries listed below
- A customized RISCV core made using verilog☆19Updated 3 years ago
- ☆16Updated last year
- Image processing on FPGA using verilog☆20Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 6 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆21Updated 3 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 7 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- ☆11Updated 6 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆35Updated 3 years ago
- ☆17Updated this week
- ☆12Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆27Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- ☆13Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 2 weeks ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆79Updated last year
- An overview of TL-Verilog resources and projects☆72Updated 10 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- ☆11Updated last week
- https://ve0x10.in/idf-notes-sra/☆11Updated 4 years ago
- ☆12Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆10Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆62Updated last year
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago