Convolutional Neural Network in C (for educational purposes)
☆31Jan 18, 2021Updated 5 years ago
Alternatives and similar repositories for nn1
Users that are interested in nn1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆11Sep 19, 2025Updated 7 months ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- Hardware and Software Co-design implementations☆15Dec 5, 2019Updated 6 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Sep 16, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆26Aug 28, 2024Updated last year
- A demo of running a custom object detection model on Raspberry Pi☆15Sep 14, 2022Updated 3 years ago
- Source Code☆27Apr 4, 2024Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆37Apr 13, 2024Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- Implementation of CORDIC Algorithms Using Verilog☆26Apr 26, 2021Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- ☆16Jul 1, 2024Updated last year
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- It is an instruction-level simulator for a single cycle MIPS processor in C++ emulating all 5 steps (Instruction Fetch, Decode, Execute, …☆11Nov 20, 2016Updated 9 years ago
- Simple demonstration of using the RISC-V Vector extension☆51Apr 18, 2024Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 months ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆18Feb 25, 2021Updated 5 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆19Sep 2, 2023Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆20Aug 19, 2024Updated last year
- ☆24Nov 11, 2025Updated 5 months ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ai_accelerator_basic_for_student (no solve)☆18Mar 27, 2020Updated 6 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- A minimal BASIC interpreter for Arduino UNO (ATmega328P).☆53Jan 18, 2026Updated 3 months ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 8 months ago
- Debian12 Boot Image (U-boot, Linux Kernel, Debian12 RootFS) for ZYBO/ZYBO-Z7/PYNQ-Z1/DE10-Nano/DE0-Nano-SoC☆21May 2, 2025Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆114Jul 9, 2023Updated 2 years ago
- My study notes and hands-on projects for CUDA-based GPU programming☆12Dec 11, 2025Updated 4 months ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆30Oct 4, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆148Apr 22, 2026Updated 2 weeks ago
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆26Aug 28, 2016Updated 9 years ago
- Video compression systems☆24Jul 17, 2014Updated 11 years ago
- ☆22Dec 8, 2024Updated last year
- Opensource HAL API Library for AVR Microcontrollers.☆12Oct 22, 2020Updated 5 years ago
- Getting started with Zephyr RTOS on BluePill STM32F103C8 board☆14Aug 24, 2023Updated 2 years ago
- C Library for ST7789 1.69 TFT LCD display☆12Jun 3, 2024Updated last year