euske / nn1Links
Convolutional Neural Network in C (for educational purposes)
☆30Updated 4 years ago
Alternatives and similar repositories for nn1
Users that are interested in nn1 are comparing it to the libraries listed below
Sorting:
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆33Updated this week
- Converting a deep neural network to integer-only inference in native C via uniform quantization and the fixed-point representation.☆26Updated 3 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆90Updated 3 months ago
- ☆35Updated 2 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆13Updated last month
- Quantization and Synthesis (Device Specific Code Generation) for ADI's MAX78000 and MAX78002 Edge AI Devices☆62Updated 5 months ago
- This repo is for Efinix TinyML platform, which offers end-to-end flow that facilitates TinyML solution deployment on Efinix FPGAs.☆73Updated 2 weeks ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Updated 8 months ago
- Simple demonstration of using the RISC-V Vector extension☆50Updated last year
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- Floating-Point Optimized On-Device Learning Library for the PULP Platform.☆37Updated last month
- Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.☆28Updated last year
- CASLab-GPU simulator in SystemC☆11Updated 5 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- ☆40Updated last year
- tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog☆56Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- ☆61Updated 8 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆25Updated this week
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 8 months ago
- This project contains a code generator that produces static C NN inference deployment code targeting tiny micro-controllers (TinyML) as r…☆29Updated 4 years ago
- CMSIS DSP Library for PULPino microcontroller☆23Updated 7 years ago
- An open-source 32-bit RISC-V soft-core processor☆44Updated 4 months ago
- Neural Engine, 16 input channels☆15Updated 3 years ago
- Learn NVDLA by SOMNIA☆42Updated 6 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆32Updated last year
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆24Updated 4 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆96Updated last year
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆91Updated 5 months ago