Alternatives and similar repositories for nn1

Users that are interested in nn1 are comparing it to the libraries listed below

• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 8 months ago
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆54Updated 4 years ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆69Updated 6 years ago
• zhehaoxu / ai-talk
  关于深度学习算法、框架、编译器、加速器的一些理解
  ☆15Updated 3 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆32Updated last year
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆49Updated last year
• pulp-platform / pulp-dsp
  ☆35Updated 2 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆12Updated 2 years ago
• pulp-platform / chimera
  ☆18Updated last month
• saursin / riscv-atom
  An open-source 32-bit RISC-V soft-core processor
  ☆41Updated 3 months ago
• siddharth23-8 / 32-bit-RISC-V-Cpu-Core
  ☆35Updated 4 years ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• ADS-ENTC / simd-processor
  Matrix multiplication accelerator on ZYNQ SoC.
  ☆12Updated 7 months ago
• brandonhamilton / GPGPU
  General Purpose Graphics Processing Unit (GPGPU) IP Core
  ☆11Updated 11 years ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated last year
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆46Updated 2 months ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆27Updated last week
• pulp-platform / ITA
  ☆60Updated 7 months ago
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆33Updated last week
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆25Updated 3 months ago
• robgiorgi / freess
  RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
  ☆27Updated last month
• pulp-platform / pulp-trainlib
  Floating-Point Optimized On-Device Learning Library for the PULP Platform.
  ☆37Updated last week
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• hubbsvtgc / LearnRISC-V
  Learn RISC-V
  ☆21Updated last year
• YqGe585 / Neural-Processing-Unit-on-FPGA
  Superscalar Out-of-Order NPU Design on FPGA
  ☆11Updated last year
• pulp-platform / redmule
  ☆89Updated last week
• PacktPublishing / Architecting-and-Building-High-Speed-SoCs
  Architecting and Building High Speed SoCs, published by Packt
  ☆29Updated 2 years ago
• dpretet / friscv
  RISCV CPU implementation in SystemVerilog
  ☆32Updated 2 months ago