euske / nn1
Convolutional Neural Network in C (for educational purposes)
☆28Updated 4 years ago
Alternatives and similar repositories for nn1:
Users that are interested in nn1 are comparing it to the libraries listed below
- Converting a deep neural network to integer-only inference in native C via uniform quantization and the fixed-point representation.☆23Updated 3 years ago
- ☆21Updated 4 years ago
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆34Updated 11 months ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆13Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆79Updated last year
- ☆45Updated 6 years ago
- ☆87Updated last year
- Simple demonstration of using the RISC-V Vector extension☆42Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆12Updated last year
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆24Updated 3 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated last month
- This is a verilog implementation of 4x4 systolic array multiplier☆50Updated 4 years ago
- A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks☆23Updated 3 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆24Updated 3 weeks ago
- Lightweight C implementation of CNNs for Embedded Systems☆60Updated 2 years ago
- CNN Accelerator for Zynq☆12Updated 5 years ago
- Implementation of CORDIC Algorithms Using Verilog☆24Updated 4 years ago
- Quantization and Synthesis (Device Specific Code Generation) for ADI's MAX78000 and MAX78002 Edge AI Devices☆59Updated last week
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- A textbook on understanding system on chip design☆34Updated last year
- Design for 4 x 4 Matrix Multiplication using Verilog☆31Updated 9 years ago
- ☆22Updated 7 months ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆46Updated 2 years ago
- ☆13Updated 4 months ago
- Low Precision(quantized) Yolov5☆37Updated last month
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆14Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated 2 months ago
- Verilog implementation of various types of CPUs☆49Updated 5 years ago