mfkiwl / E203_dma

Related projects ⓘ

Alternatives and complementary repositories for E203_dma

• wanderingnail / AXI_DMA
  ☆16Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆37Updated 4 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆15Updated 10 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆29Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆30Updated last year
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆12Updated 7 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆33Updated 9 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆20Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆33Updated 2 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆17Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆28Updated 2 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆29Updated 6 years ago
• ym31433 / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆18Updated 7 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 3 years ago
• fangyzh26 / FIFO
  包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）
  ☆20Updated 2 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆27Updated last year
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆22Updated 5 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆18Updated 2 years ago
• GJigar / ZYNQ_CNN
  ☆16Updated 2 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆35Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 11 years ago
• raiyyanfaisal09 / Router1X3_RTL_Design
  - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…
  ☆10Updated 5 years ago