Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
☆16Jun 5, 2023Updated 3 years ago
Alternatives and similar repositories for SEU-ASIC-IOT-ECGAI
Users that are interested in SEU-ASIC-IOT-ECGAI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 6 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆12Sep 30, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation network trimming using pytorch☆15Apr 20, 2020Updated 6 years ago
- This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologi…☆12Oct 19, 2024Updated 2 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- Lecture Material on Deep Learning Inference using FPGA☆13Jun 9, 2020Updated 6 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA☆22Oct 17, 2022Updated 4 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆15Aug 26, 2021Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆31Nov 5, 2021Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆13Apr 8, 2023Updated 3 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆19Feb 27, 2021Updated 5 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆16Nov 4, 2022Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Aug 28, 2021Updated 5 years ago
- EE 287 2012 Fall☆34Mar 11, 2013Updated 13 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆11Mar 22, 2022Updated 4 years ago
- ☆11Jul 25, 2018Updated 8 years ago
- ☆14Oct 24, 2022Updated 4 years ago
- Python package that allows both automated and customized treatment of missing values in datasets☆10Dec 29, 2022Updated 3 years ago
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 6 years ago
- [ICML 2024] Boundary Exploration for Bayesian Optimization With Unknown Physical Constraints☆11May 18, 2024Updated 2 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 5 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- The CTGViewer: display cardiotocography (CTG) records -- fetal heart rate and uterine contractions.☆11Feb 22, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- 机器人使用了Xilinx的SPARTAN-6系列芯片以及ISE设计工具对机器人控制电路进行了设计和仿真,验证了电路的正确性和可靠性。同时机器人使用了温湿度传感器、人体感应传感器、超声波传感器、震动传感器、有毒气体传感器等,可以对灾区的环境和受困人员进行多方面的检测和响应。还…☆12Nov 15, 2023Updated 2 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 6 years ago
- Quadratic program minimizing risk while maintaining an expected return with the addition of rollover in the foreign exchange market☆12Nov 2, 2016Updated 9 years ago
- The PE for the second generation CGRA (garnet).☆18Updated this week
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 8 years ago