SivannaKing / SEU-ASIC-IOT-ECGAI
Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
☆17Updated last year
Alternatives and similar repositories for SEU-ASIC-IOT-ECGAI:
Users that are interested in SEU-ASIC-IOT-ECGAI are comparing it to the libraries listed below
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆23Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- cnn accelerator in vivado HLS☆9Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆32Updated last year
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- ☆26Updated 2 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆26Updated 3 weeks ago