Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
☆14Aug 25, 2023Updated 2 years ago
Alternatives and similar repositories for RTL_library_of_basic_hardware_units
Users that are interested in RTL_library_of_basic_hardware_units are comparing it to the libraries listed below
Sorting:
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆37Aug 9, 2025Updated 6 months ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- ☆12Jul 24, 2018Updated 7 years ago
- ☆18Oct 3, 2024Updated last year
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- [DATE'23] The official code for paper <CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory>☆23Jan 19, 2026Updated last month
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.☆24Sep 11, 2023Updated 2 years ago
- An automated HDC platform☆11Updated this week
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆58Nov 22, 2023Updated 2 years ago
- Curated content for DNN approximation, acceleration ... with a focus on hardware accelerator and deployment☆27May 15, 2024Updated last year
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- ☆29Nov 5, 2021Updated 4 years ago
- ☆33Nov 6, 2024Updated last year
- Boolean Hypervectors with various operators for experiments in hyperdimensional computing (HDC).☆31Jan 7, 2026Updated last month
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆33May 20, 2020Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- ☆35Dec 22, 2025Updated 2 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Zircon CPU in 2024☆11Nov 21, 2025Updated 3 months ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- Accelerator for Hyperdimensional Computing (HDC)☆35May 5, 2024Updated last year
- WaferLLM: Large Language Model Inference at Wafer Scale☆90Jan 7, 2026Updated last month
- Verilog implementation of MC68851 Memory Management Unit☆13Feb 26, 2018Updated 8 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- ☆57Nov 29, 2025Updated 3 months ago
- ☆10Aug 2, 2021Updated 4 years ago
- Human activity recognition using hyperdimensional computing based on Kinect's skeleton data☆11Jun 5, 2017Updated 8 years ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆13May 16, 2024Updated last year
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- ☆10Jan 3, 2022Updated 4 years ago