I-Doctor / RTL_library_of_basic_hardware_unitsLinks
Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
☆13Updated 2 years ago
Alternatives and similar repositories for RTL_library_of_basic_hardware_units
Users that are interested in RTL_library_of_basic_hardware_units are comparing it to the libraries listed below
Sorting:
- ☆35Updated 5 years ago
- ☆19Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 7 months ago
- Model LLM inference on single-core dataflow accelerators☆18Updated last month
- MICRO22 artifact evaluation for Sparseloop☆47Updated 3 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆48Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 3 years ago
- ☆57Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- A co-design architecture on sparse attention☆55Updated 4 years ago
- ☆42Updated last year
- bitfusion verilog implementation☆12Updated 3 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- MICRO 2024 Evaluation Artifact for FuseMax☆16Updated last year
- ☆20Updated 8 months ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆37Updated 6 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Updated 10 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆71Updated last month
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆87Updated 9 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- ☆13Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆72Updated 4 months ago