Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
☆17Aug 25, 2023Updated 3 years ago
Alternatives and similar repositories for RTL_library_of_basic_hardware_units
Users that are interested in RTL_library_of_basic_hardware_units are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆45Aug 9, 2025Updated last year
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆15Nov 19, 2023Updated 2 years ago
- ☆13Jul 24, 2018Updated 8 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆19Aug 26, 2024Updated 2 years ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆14Jun 18, 2025Updated last year
- [DATE'23] The official code for paper <CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory>☆25Nov 2, 2026Updated last week
- [HPCA 2026 Best Paper Candidate] Official implementation of "Focus: A Streaming Concentration Architecture for Efficient Vision-Language …☆72Feb 8, 2026Updated 9 months ago
- ☆10Feb 26, 2026Updated 8 months ago
- [DAC 2026] FlashFPS☆17Jun 1, 2026Updated 5 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- Efficient Expert Pruning for Sparse Mixture-of-Experts Language Models: Enhancing Performance and Reducing Inference Costs☆25Nov 11, 2025Updated last year
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆34Mar 7, 2024Updated 2 years ago
- Code implementation of DuoGPT (NeurIPS 2025, https://arxiv.org/abs/2506.20194)☆10Sep 23, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆88Aug 28, 2023Updated 3 years ago
- Major project - kannada LLM for farmers☆12May 20, 2024Updated 2 years ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆15May 16, 2024Updated 2 years ago
- Artifacts of ASPLOS'26 paper titled "FastTTS: Accelerating Test-Time Scaling for Edge LLM Reasoning"☆14Mar 9, 2026Updated 8 months ago
- ☆20Jun 4, 2026Updated 5 months ago
- HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing☆15Sep 2, 2026Updated 2 months ago
- ☆19Oct 3, 2024Updated 2 years ago
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆14Jul 9, 2020Updated 6 years ago
- LoCaLUT_AE☆13Dec 8, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Jul 7, 2020Updated 6 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆136Jun 27, 2023Updated 3 years ago
- Artifact of Chimera☆18May 6, 2025Updated last year
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆34Jul 4, 2024Updated 2 years ago
- Boolean Hypervectors with various operators for experiments in hyperdimensional computing (HDC).☆36Mar 5, 2026Updated 8 months ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆22Nov 6, 2025Updated last year
- [ASPLOS 2026] M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization.☆17Jan 29, 2026Updated 9 months ago
- ☆42Oct 21, 2025Updated last year
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆25Mar 17, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆127Nov 17, 2023Updated 2 years ago
- ☆19Nov 11, 2024Updated 2 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Apr 9, 2019Updated 7 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.☆13Jan 9, 2020Updated 6 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- ☆16Nov 3, 2026Updated last week
Are these results useful?