jeshraghian / snn-acceleratorLinks
☆25Updated 3 years ago
Alternatives and similar repositories for snn-accelerator
Users that are interested in snn-accelerator are comparing it to the libraries listed below
Sorting:
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆61Updated 2 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆85Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- Fully opensource spiking neural network accelerator☆151Updated 2 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆59Updated 5 months ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆18Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆59Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆12Updated 2 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆25Updated 6 years ago
- FPGA Design of a Spiking Neural Network.☆42Updated last year
- ☆19Updated 4 years ago
- ☆48Updated last year
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆187Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆13Updated last year
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆69Updated 2 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- ☆17Updated 4 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆56Updated last year
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- SNN on FPGA☆10Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆18Updated 2 years ago
- A repository FPGA-friendly SNN models☆33Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- Spiking Neural Network RTL Implementation☆58Updated 4 years ago
- Verilog and Python drivers and APIs for Neurram 48-core chip☆40Updated 3 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago