A bit-level sparsity-awared multiply-accumulate process element.
☆21Jul 9, 2024Updated 2 years ago
Alternatives and similar repositories for Bitlet-PE
Users that are interested in Bitlet-PE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆20Mar 21, 2023Updated 3 years ago
- ☆19Nov 11, 2024Updated last year
- Open-source of MSD framework☆16Sep 12, 2023Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ☆162Jul 19, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆125Nov 17, 2023Updated 2 years ago
- HB-NPU simulator runs the HB-DRAM PNM accelerator, HB-NPU, based on DRAMsim3 open source DRAM simulator.☆14Oct 21, 2026Updated 2 weeks ago
- c++ version of ViT☆13Nov 13, 2022Updated 3 years ago
- BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)☆41Jan 12, 2021Updated 5 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆14May 9, 2022Updated 4 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆96Apr 26, 2026Updated 6 months ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆17Aug 25, 2023Updated 3 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆41Oct 21, 2025Updated last year
- [HPCA 2026 Best Paper Candidate] Official implementation of "Focus: A Streaming Concentration Architecture for Efficient Vision-Language …☆68Feb 8, 2026Updated 8 months ago
- HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing☆15Sep 2, 2026Updated 2 months ago
- ☆12Nov 24, 2023Updated 2 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆136Jun 27, 2023Updated 3 years ago
- Model LLM inference on single-core dataflow accelerators☆22Dec 16, 2025Updated 10 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆19Feb 27, 2021Updated 5 years ago
- Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]☆17Nov 11, 2025Updated 11 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆34Mar 7, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆40Mar 11, 2026Updated 7 months ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆22Nov 6, 2025Updated 11 months ago
- Reimplementation of paper EIE by Stanford Song Han☆10Mar 18, 2021Updated 5 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆56Mar 24, 2024Updated 2 years ago
- ViTALiTy (HPCA'23) Code Repository☆25Mar 13, 2023Updated 3 years ago
- ☆27Apr 3, 2026Updated 7 months ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 6 years ago
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆10Apr 19, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Homulator is a cycle-accurate simulator tailored for Fully Homomorphic Encryption (FHE) accelerators. It offers detailed architectural ru…☆10Jul 30, 2024Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆19Aug 26, 2024Updated 2 years ago
- ☆10Jul 4, 2022Updated 4 years ago
- Simulator for BitFusion☆104Aug 6, 2020Updated 6 years ago
- This repo contains the code for studying the interplay between quantization and sparsity methods☆26Feb 26, 2025Updated last year
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆44Aug 9, 2025Updated last year