A bit-level sparsity-awared multiply-accumulate process element.
☆21Jul 9, 2024Updated 2 years ago
Alternatives and similar repositories for Bitlet-PE
Users that are interested in Bitlet-PE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Mar 21, 2023Updated 3 years ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- ☆41Oct 21, 2025Updated 10 months ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆91Apr 26, 2026Updated 4 months ago
- ☆158Jul 19, 2025Updated last year
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆20Nov 6, 2025Updated 9 months ago
- ☆124Nov 17, 2023Updated 2 years ago
- ☆19Nov 11, 2024Updated last year
- c++ version of ViT☆13Nov 13, 2022Updated 3 years ago
- ☆20Apr 23, 2025Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Ef ficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- bitfusion verilog implementation☆13Feb 21, 2022Updated 4 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆15Aug 25, 2023Updated 3 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- An energy simulation framework for BPTT-based SNN inference and training.☆17Sep 6, 2023Updated 2 years ago
- [HPCA 2026 Best Paper Candidate] Official implementation of "Focus: A Streaming Concentration Architecture for Efficient Vision-Language …☆63Feb 8, 2026Updated 6 months ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆14May 9, 2022Updated 4 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆42Aug 9, 2025Updated last year
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆19Mar 6, 2025Updated last year
- Model LLM inference on single-core dataflow accelerators☆22Dec 16, 2025Updated 8 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆15Jun 28, 2021Updated 5 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 3 years ago
- ☆24May 14, 2025Updated last year
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Nov 8, 2021Updated 4 years ago
- ☆12Nov 24, 2023Updated 2 years ago
- Python implementation of the Fully Homomorphic Encryption Scheme TFHE☆19Jun 19, 2023Updated 3 years ago
- This repo contains the code for studying the interplay between quantization and sparsity methods☆26Feb 26, 2025Updated last year
- ☆24Apr 3, 2026Updated 5 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆18Jul 7, 2021Updated 5 years ago
- Artifact for Oaken: Fast and Efficient LLM Serving with Online-Offline Hybrid KV Cache Quantization☆18May 9, 2025Updated last year
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]☆16Nov 11, 2025Updated 9 months ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Feb 22, 2024Updated 2 years ago
- BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)☆41Jan 12, 2021Updated 5 years ago
- ☆20Jan 2, 2026Updated 8 months ago