2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
☆72Apr 13, 2024Updated 2 years ago
Alternatives and similar repositories for soc-design-and-planning-nasscom-vsd
Users that are interested in soc-design-and-planning-nasscom-vsd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25Oct 3, 2025Updated 10 months ago
- ☆21Nov 8, 2025Updated 9 months ago
- Understand how TCL scripting automates ASIC synthesis and timing analysis using Yosys & OpenTimer, with CSV/Excel inputs acting as fr…☆19Oct 26, 2025Updated 9 months ago
- This repository is a detailed summary of RTL design using sky130 PDK organized by VLSI System Design☆28Jun 1, 2025Updated last year
- Semiconductor Packaging Fundamentals☆36May 19, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆44Mar 28, 2022Updated 4 years ago
- ☆25Nov 11, 2025Updated 9 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆21Aug 19, 2024Updated last year
- ☆42Jun 24, 2026Updated last month
- This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the A…☆16Sep 9, 2025Updated 11 months ago
- ☆14Sep 29, 2024Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆84Nov 26, 2020Updated 5 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆14Apr 13, 2025Updated last year
- ☆21Aug 4, 2022Updated 4 years ago
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆41Sep 21, 2023Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆33Jul 21, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V Dual-Issue RV32I Core in SystemVerilog☆24Updated this week
- Hardware and Software Co-design implementations☆16Dec 5, 2019Updated 6 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆18Sep 16, 2018Updated 7 years ago
- IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator tape…☆41Jul 10, 2026Updated last month
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆62Jan 18, 2025Updated last year
- ☆19Nov 1, 2025Updated 9 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆101Apr 25, 2026Updated 3 months ago
- Active Learning Interface for Circuits and Electronics☆20Feb 18, 2023Updated 3 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆66Mar 21, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆23Jul 5, 2021Updated 5 years ago
- ☆19Sep 16, 2022Updated 3 years ago
- [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq and other FPGA tutorials, ready to copy and paste.☆85Mar 31, 2026Updated 4 months ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆32Jul 31, 2026Updated 2 weeks ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 6 months ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆31Aug 28, 2024Updated last year
- Design and Simulation of 1K * 32 bit SRAM memory design.☆23Dec 15, 2021Updated 4 years ago