fayizferosh / soc-design-and-planning-nasscom-vsdLinks
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
☆22Updated last year
Alternatives and similar repositories for soc-design-and-planning-nasscom-vsd
Users that are interested in soc-design-and-planning-nasscom-vsd are comparing it to the libraries listed below
Sorting:
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 9 months ago
- ☆13Updated 8 months ago
- ☆10Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Architectural design of data router in verilog☆30Updated 5 years ago
- ☆17Updated 3 weeks ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- ☆17Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆18Updated last week
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 6 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- ☆15Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆78Updated last year
- ☆30Updated last year
- ☆12Updated 2 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated last year
- RTL to GDS via Cadence Tools☆11Updated 3 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆9Updated 9 months ago
- System Verilog using Functional Verification☆12Updated last year
- ☆16Updated last year
- opensource EDA tool flor VLSI design☆33Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- ☆15Updated last year
- ☆41Updated 3 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago