fayizferosh / soc-design-and-planning-nasscom-vsdLinks
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
☆25Updated last year
Alternatives and similar repositories for soc-design-and-planning-nasscom-vsd
Users that are interested in soc-design-and-planning-nasscom-vsd are comparing it to the libraries listed below
Sorting:
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 10 months ago
- ☆11Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆19Updated last month
- This repo provide an index of VLSI content creators and their materials☆152Updated 10 months ago
- ☆113Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆94Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆83Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 7 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆19Updated last year
- ☆13Updated 9 months ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- ☆12Updated 3 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- opensource EDA tool flor VLSI design☆33Updated last year
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆14Updated last year
- ☆20Updated last year
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆22Updated last week
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆15Updated 2 years ago
- ☆17Updated 2 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆50Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- System Verilog using Functional Verification☆12Updated last year
- ☆41Updated last year