fayizferosh / soc-design-and-planning-nasscom-vsdLinks
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
☆26Updated last year
Alternatives and similar repositories for soc-design-and-planning-nasscom-vsd
Users that are interested in soc-design-and-planning-nasscom-vsd are comparing it to the libraries listed below
Sorting:
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆12Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- ☆13Updated 2 years ago
- ☆114Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆24Updated last year
- This repo provide an index of VLSI content creators and their materials☆156Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- ☆15Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆89Updated 2 years ago
- opensource EDA tool flor VLSI design☆33Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆21Updated last week
- ☆17Updated 2 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- Design Verification Engineer interview preparation guide.☆33Updated last month
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated last month
- ☆12Updated 4 months ago
- ☆21Updated last year
- ☆17Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆13Updated 9 months ago
- RTL to GDS via Cadence Tools☆13Updated 3 years ago
- ☆13Updated 11 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆115Updated 3 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆62Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆107Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆40Updated 3 years ago