2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
☆35Apr 13, 2024Updated last year
Alternatives and similar repositories for soc-design-and-planning-nasscom-vsd
Users that are interested in soc-design-and-planning-nasscom-vsd are comparing it to the libraries listed below
Sorting:
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year
- ☆18Nov 11, 2025Updated 3 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- ☆14Sep 16, 2022Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Nov 26, 2020Updated 5 years ago
- Hardware and Software Co-design implementations☆15Dec 5, 2019Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆44Sep 26, 2023Updated 2 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆23Aug 28, 2024Updated last year
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- Design Verification Engineer interview preparation guide.☆44Jul 20, 2025Updated 7 months ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- ☆35Nov 24, 2021Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆110Jul 9, 2023Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Nov 24, 2025Updated 3 months ago
- ☆11Sep 8, 2021Updated 4 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆12Aug 26, 2024Updated last year
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Mar 6, 2025Updated last year
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- Developed an algorithm for Attitude Determination and control of a 1DOF 1U Cubesat.☆13Jul 25, 2021Updated 4 years ago
- 1U CubeSat engineering model solar panels hardware project.☆12Dec 19, 2020Updated 5 years ago
- Native powerpc-apple-darwin8.11.0 gcc and friends.☆11Mar 25, 2025Updated 11 months ago
- Our pipe dream☆13May 9, 2023Updated 2 years ago
- Alaska Research CubeSat Attitude Control and Determination System flight code☆10Jan 6, 2017Updated 9 years ago
- Verified visual schematics for all SKY130 Cells☆12Feb 2, 2026Updated last month
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 5 months ago
- ☆14Apr 13, 2025Updated 10 months ago
- ☆11Nov 17, 2025Updated 3 months ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆18Nov 18, 2025Updated 3 months ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 5 years ago
- All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.☆25Dec 14, 2025Updated 2 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆57Jul 9, 2021Updated 4 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆52Jan 4, 2022Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆49Mar 2, 2026Updated last week