arunkpv / vsd-hdp
☆15Updated 7 months ago
Alternatives and similar repositories for vsd-hdp:
Users that are interested in vsd-hdp are comparing it to the libraries listed below
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 6 months ago
- ☆14Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆14Updated 10 months ago
- Architectural design of data router in verilog☆30Updated 5 years ago
- ☆12Updated 2 weeks ago
- ☆17Updated 2 years ago
- ☆14Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- ☆14Updated last year
- ☆16Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 3 years ago
- ☆39Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆55Updated 10 months ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- ☆16Updated 11 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆66Updated last year
- ☆40Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆8Updated 2 years ago
- ☆16Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- Complete tutorial code.☆16Updated 10 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago