arunkpv / vsd-hdpView external linksLinks
☆18Nov 11, 2025Updated 3 months ago
Alternatives and similar repositories for vsd-hdp
Users that are interested in vsd-hdp are comparing it to the libraries listed below
Sorting:
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year
- ☆14Sep 16, 2022Updated 3 years ago
- This repo will show how to build FFTW on Zynq☆15Jan 31, 2025Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Nov 25, 2024Updated last year
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 4 years ago
- opensource EDA tool flor VLSI design☆36Sep 17, 2023Updated 2 years ago
- Implementation of RISC-V RV32I☆28Aug 30, 2022Updated 3 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆31Jul 21, 2025Updated 6 months ago
- ☆47Apr 7, 2024Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- Ressources for Boinformatics Trainings☆12Nov 20, 2023Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- AMD Xilinx University Program Vivado tutorial☆43Feb 13, 2023Updated 3 years ago
- Map large-scale single cells to the exact spatial locations☆15Jun 12, 2025Updated 8 months ago
- ☆13Sep 29, 2024Updated last year
- Scripts for Digital Design flow control.☆16Oct 30, 2025Updated 3 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Aug 26, 2024Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- Main repository of the Flint project for Spark and Amazon EMR.☆11Jan 31, 2020Updated 6 years ago
- ☆12Apr 8, 2021Updated 4 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- ☆13Jan 30, 2026Updated 2 weeks ago
- ☆11Nov 17, 2025Updated 2 months ago
- ☆11Jan 2, 2023Updated 3 years ago
- ☆10Mar 20, 2021Updated 4 years ago
- ☆10Nov 30, 2024Updated last year
- Quadcopter control and pole balancing using deep reinforcement learning and hand gestures on ultra96☆10Oct 31, 2023Updated 2 years ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆13Sep 18, 2025Updated 4 months ago
- Themis MapReduce and TritonSort☆11Nov 2, 2017Updated 8 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- ☆41Feb 28, 2022Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Jan 4, 2022Updated 4 years ago
- a mini TPU with floating point arithmetic☆49Dec 22, 2025Updated last month
- Design of miller compensated 2 stage opamp using open source SKY130PDK☆13Jun 18, 2025Updated 7 months ago
- ☆14Sep 27, 2022Updated 3 years ago
- Scripts used to generate the ClinVar conflicting classifications dataset on Kaggle☆16Jul 28, 2020Updated 5 years ago
- ☆14Jun 22, 2023Updated 2 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago