arunkpv / vsd-hdpLinks
☆17Updated 2 months ago
Alternatives and similar repositories for vsd-hdp
Users that are interested in vsd-hdp are comparing it to the libraries listed below
Sorting:
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆26Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 11 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆88Updated 2 years ago
- ☆114Updated last year
- ☆41Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆20Updated 2 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 2 years ago
- opensource EDA tool flor VLSI design☆33Updated last year
- SystemVerilog Tutorial☆159Updated 2 months ago
- ☆17Updated last year
- ☆15Updated 2 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated last year
- ☆162Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- ☆12Updated 4 months ago
- ☆11Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆154Updated 11 months ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆13Updated 8 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆45Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆105Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆16Updated 2 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆12Updated 11 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆104Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆51Updated last year
- UVM and System Verilog Manuals☆43Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year