mean9park / BitFusion-verilogLinks
bitfusion verilog implementation
☆12Updated 3 years ago
Alternatives and similar repositories for BitFusion-verilog
Users that are interested in BitFusion-verilog are comparing it to the libraries listed below
Sorting:
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- A co-design architecture on sparse attention☆52Updated 4 years ago
- Model LLM inference on single-core dataflow accelerators☆14Updated last month
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- ☆51Updated 2 months ago
- ☆45Updated 2 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- ☆31Updated this week
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆29Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆35Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- ☆48Updated 4 years ago
- ☆18Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆24Updated 6 months ago
- ☆47Updated last month
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆149Updated 4 months ago