Alternatives and similar repositories for BitFusion-verilog

Users that are interested in BitFusion-verilog are comparing it to the libraries listed below

• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 10 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 2 months ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 3 months ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆27Updated last year
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆11Updated 3 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆44Updated last year
• booniebears / CoMN
  ☆15Updated last year
• RuokaiYin / LoAS
  LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
  ☆11Updated 2 months ago
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 8 months ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• I-Doctor / RTL_library_of_basic_hardware_units
  Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …
  ☆11Updated last year
• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆11Updated last year
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆13Updated 3 years ago
• chiragsakhuja / spotlight
  ☆16Updated 2 years ago
• abdelfattah-lab / BitMoD-HPCA-25
  ☆41Updated 5 months ago
• jeffreyyu0602 / quantized-training
  ☆27Updated this week
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆48Updated 4 years ago
• lsq314 / SpMM_TCAD
  ☆17Updated 8 months ago
• MXHX7199 / ICCV_2021_AFP
  AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.
  ☆12Updated 3 years ago
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆23Updated last year
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• hatsu3 / Sanger
  ☆45Updated 3 years ago
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆14Updated 10 months ago