Alternatives and similar repositories for XNOR-net-Binary-connect:

Users that are interested in XNOR-net-Binary-connect are comparing it to the libraries listed below

• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆44Updated 6 years ago
• hqjenny / CoDeNet
  ☆19Updated 3 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆47Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated last year
• maomran / softmax
  Verilog implementation of Softmax function
  ☆54Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• abdelfattah-lab / BRAMAC
  ☆10Updated last month
• racosa / cnn-accelerator
  A Convolutional Neural Network (CNN) hardware accelerator for image recognition
  ☆10Updated 5 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆45Updated 7 years ago
• maao666 / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆37Updated 4 months ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆29Updated last year
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• jgoeders / dac_sdc_2021_designs
  ☆19Updated 2 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆26Updated 8 months ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆65Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆31Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆54Updated 3 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆22Updated 3 years ago
• awai54st / LUTNet
  ☆56Updated 4 years ago