Alternatives and similar repositories for XNOR-net-Binary-connect:

Users that are interested in XNOR-net-Binary-connect are comparing it to the libraries listed below

• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆50Updated 6 years ago
• abdelfattah-lab / BRAMAC
  ☆10Updated 4 months ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 7 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated last year
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• hqjenny / CoDeNet
  ☆19Updated 4 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 4 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆91Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆43Updated last month
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆137Updated 5 years ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆14Updated 4 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆30Updated 5 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 4 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated last week
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• ztgao / ConvNN_FPGA_Accelerator
  ☆14Updated 9 years ago