IBM / mini-era
Mini-ERA is a simplified still-representative version of the main ERA workload.
☆14Updated 2 years ago
Alternatives and similar repositories for mini-era:
Users that are interested in mini-era are comparing it to the libraries listed below
- ☆89Updated 11 months ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆117Updated 4 years ago
- ☆84Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- ☆52Updated this week
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆49Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆67Updated 5 months ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆38Updated 6 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- ☆10Updated 2 years ago
- CGRA Compilation Framework☆82Updated last year
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 6 months ago
- Falcon Merlin Compiler☆38Updated 4 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆85Updated 3 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆20Updated last week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 6 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 2 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last month