FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
☆50Feb 26, 2025Updated last year
Alternatives and similar repositories for FlexASR
Users that are interested in FlexASR are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆295Oct 30, 2025Updated 4 months ago
- Neural Network Quantization With Fractional Bit-widths☆11Feb 19, 2021Updated 5 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago
- TQT's pytorch implementation.☆21Dec 17, 2021Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆406Mar 17, 2026Updated last week
- ☆24Apr 20, 2024Updated last year
- ☆12Aug 12, 2022Updated 3 years ago
- ☆47Nov 23, 2023Updated 2 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Feb 8, 2023Updated 3 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆50Updated this week
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- [ICCV 2023] I-ViT: Integer-only Quantization for Efficient Vision Transformer Inference☆200Sep 2, 2024Updated last year
- DeiT implementation for Q-ViT☆25Apr 21, 2025Updated 11 months ago
- A collection of tutorials for the fpgaConvNet framework.☆48Sep 20, 2024Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Jul 14, 2019Updated 6 years ago
- RTL implementation of Flex-DPE.☆116Feb 22, 2020Updated 6 years ago
- ☆12Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- A Modeling and Verification Platform for SoCs using ILAs☆82Jul 3, 2024Updated last year
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Mar 16, 2022Updated 4 years ago
- ☆16Jan 18, 2025Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 10 months ago
- ☆27Mar 19, 2021Updated 5 years ago
- HLS for Networks-on-Chip☆39Feb 18, 2021Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42May 24, 2020Updated 5 years ago
- The PyTorch implementation of Learned Step size Quantization (LSQ) in ICLR2020 (unofficial)☆139Nov 19, 2020Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last week
- A DSL for Systolic Arrays☆84Dec 14, 2018Updated 7 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- [ICML'21 Oral] I-BERT: Integer-only BERT Quantization☆266Jan 29, 2023Updated 3 years ago
- An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.☆14Feb 3, 2025Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 5 years ago