Alternatives and similar repositories for FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm

Users that are interested in FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm are comparing it to the libraries listed below

• vitaliikulin / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆20Updated 5 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆46Updated 9 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 3 years ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆12Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆92Updated 3 years ago
• ykqiu / image-processing
  Real-Time Image Processing for ASIC/FGPA
  ☆21Updated 3 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆67Updated 8 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆57Updated 4 months ago
• Grootzz / Verilog-FIR
  FIR implemention with Verilog
  ☆50Updated 6 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆67Updated 3 weeks ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆50Updated 6 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆28Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆50Updated 4 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆80Updated last year
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• uestcXJW / FIR_Filter
  A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB
  ☆10Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆31Updated 5 years ago
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆32Updated 6 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆18Updated 5 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆56Updated 2 years ago
• muneeb-mbytes / uvm_tb_arch_doc_py
  A python project to automatically generate the UVM testbench document.
  ☆21Updated last year
• antmicro / openssd-nvme
  ☆32Updated 4 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆44Updated 8 years ago