sfox14 / darknet-zynq
Accelerating DNN inference and training on Zynq
☆15Updated 4 years ago
Alternatives and similar repositories for darknet-zynq:
Users that are interested in darknet-zynq are comparing it to the libraries listed below
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- ☆43Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆26Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆19Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆55Updated 3 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- 中文:☆95Updated 5 years ago
- ☆60Updated 6 years ago
- Residual Binarized Neural Network☆44Updated 6 years ago
- ☆19Updated 7 years ago
- Pynq computer vision examples with an OV5640 camera☆44Updated 4 years ago