sfox14 / darknet-zynqLinks
Accelerating DNN inference and training on Zynq
☆16Updated 5 years ago
Alternatives and similar repositories for darknet-zynq
Users that are interested in darknet-zynq are comparing it to the libraries listed below
Sorting:
- 2019 SEU-Xilinx Summer School☆50Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆85Updated 6 years ago
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆26Updated 3 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- 中文:☆103Updated 5 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆99Updated last year
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆63Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- ☆26Updated 2 years ago
- This is just for Takk_Zynq_Labs test.☆26Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆17Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆38Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆75Updated last year
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- ☆55Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- Face recognition, computer vision, deep learning, PYNQ, Movidius NCS☆61Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- ☆90Updated 5 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago