sfox14 / darknet-zynqLinks
Accelerating DNN inference and training on Zynq
☆15Updated 4 years ago
Alternatives and similar repositories for darknet-zynq
Users that are interested in darknet-zynq are comparing it to the libraries listed below
Sorting:
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- ☆26Updated 2 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆55Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆23Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆39Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- ☆33Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 8 months ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- ☆46Updated 7 years ago
- Zynq-7000 DPU TRD☆45Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆82Updated 3 years ago
- ☆33Updated 6 years ago
- ☆44Updated 2 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 5 years ago