Alternatives and similar repositories for riscvassembler

Users that are interested in riscvassembler are comparing it to the libraries listed below

• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated this week
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆19Updated 10 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 7 months ago
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆21Updated 5 months ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆48Updated last year
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated last year
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated 2 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆51Updated this week
• chipsalliance / diplomacy
  ☆21Updated 5 months ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆50Updated 2 years ago
• OpenXiangShan / Utility
  ☆14Updated last week
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• abs-tudelft / Tydi-Chisel
  ☆18Updated 5 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• ucb-bar / testchipip
  ☆86Updated 2 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆238Updated last year
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 5 months ago
• sangwoojun / ulx3s_bsv
  Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga
  ☆15Updated 5 months ago
• merledu / Scala-Chisel-Learning-Journey
  This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…
  ☆13Updated 3 weeks ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 3 months ago
• VeriScala / VeriScala
  ☆15Updated 8 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆27Updated last week
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆14Updated 7 months ago
• stanford-ppl / argon
  Scala staging framework
  ☆16Updated 7 years ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆39Updated last week
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆110Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆63Updated 2 weeks ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago