Alternatives and similar repositories for riscvassembler

Users that are interested in riscvassembler are comparing it to the libraries listed below

• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆20Updated 2 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 weeks ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆84Updated this week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated last month
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆14Updated 4 months ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated last year
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆18Updated 6 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆19Updated 3 months ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last week
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 5 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆42Updated last week
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆48Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 3 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆35Updated last week
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆11Updated 3 months ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆25Updated this week
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• euphoric-hardware / rtl-simulation-reading
  ☆14Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 8 months ago
• iscas-tis / CHA
  ☆19Updated 10 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated 2 years ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆32Updated 2 weeks ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated last month