carlosedp / riscvassembler
A RISC-V assembler library for Scala/Chisel HDL projects
☆13Updated 2 weeks ago
Alternatives and similar repositories for riscvassembler:
Users that are interested in riscvassembler are comparing it to the libraries listed below
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆84Updated last week
- A Scala library for Context-Dependent Environments☆47Updated 11 months ago
- Wrapper for ETH Ariane Core☆19Updated 2 weeks ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆18Updated 2 months ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga☆11Updated 3 weeks ago
- ☆17Updated last week
- Network components (NIC, Switch) for FireBox☆16Updated 5 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 2 months ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 9 months ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆30Updated this week
- Useful utilities for BAR projects☆31Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Chisel Fixed-Point Arithmetic Library☆13Updated 2 months ago
- This repo includes XiangShan's function units☆18Updated this week
- Chisel/Firrtl execution engine☆153Updated 7 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆47Updated 2 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆39Updated 5 months ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆17Updated 4 months ago
- An implementation of RISC-V☆28Updated last week
- Open-source non-blocking L2 cache☆38Updated this week
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- ☆11Updated 3 years ago
- ☆13Updated last week
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- an experiment to run plugin in firtool pipeline☆9Updated last year
- Chisel HDL example applications☆30Updated 2 years ago
- ☆23Updated 4 years ago
- Open-source high-performance non-blocking cache☆78Updated last week