carlosedp / riscvassembler
A RISC-V assembler library for Scala/Chisel HDL projects
☆13Updated 3 months ago
Alternatives and similar repositories for riscvassembler:
Users that are interested in riscvassembler are comparing it to the libraries listed below
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆84Updated this week
- An RTL generator for a last-level shared inclusive TileLink cache controller☆16Updated last month
- Wrapper for ETH Ariane Core☆19Updated 6 months ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆18Updated last month
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 7 months ago
- Useful utilities for BAR projects☆31Updated last year
- A Scala library for Context-Dependent Environments☆47Updated 9 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆47Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- ☆17Updated this week
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated last year
- an experiment to run plugin in firtool pipeline☆9Updated last year
- ☆11Updated 3 years ago
- An implementation of RISC-V☆21Updated last week
- Simple UVM environment for experimenting with Verilator.☆17Updated last month
- Block-diagram style digital logic visualizer☆23Updated 9 years ago
- This repo includes XiangShan's function units☆18Updated this week
- Chisel Fixed-Point Arithmetic Library☆11Updated last month
- Network components (NIC, Switch) for FireBox☆17Updated 3 months ago
- Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga☆10Updated 11 months ago
- Chisel/Firrtl execution engine☆154Updated 6 months ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆36Updated 3 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆26Updated last year
- ☆26Updated 4 years ago