Alternatives and similar repositories for rv32cpu:

Users that are interested in rv32cpu are comparing it to the libraries listed below

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 4 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆29Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated last month
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆40Updated 2 months ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆63Updated 7 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago