Alternatives and similar repositories for rv32cpu

Users that are interested in rv32cpu are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆43Updated 6 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• open-design / riscv-soc-cores
  ☆40Updated 4 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆123Updated 9 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 13 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 9 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 10 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆96Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated 10 months ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated 10 months ago