A RISC-V processor
☆15Dec 11, 2018Updated 7 years ago
Alternatives and similar repositories for rv32cpu
Users that are interested in rv32cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- uRV RISC-V core☆19Sep 29, 2015Updated 10 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆11Apr 30, 2023Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- Clarvi simple RISC-V processor for teaching☆57Aug 25, 2017Updated 8 years ago
- A synthesizable picmicro-midrange clone for FPGAs☆13Nov 8, 2019Updated 6 years ago
- DE1SoC VGA and Audio☆10Jan 11, 2017Updated 9 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- Simple BLE demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)☆16Dec 12, 2020Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Jul 10, 2016Updated 9 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- Programmable multichannel ADPCM decoder for FPGA☆25Dec 28, 2020Updated 5 years ago
- A simple RISC-V core, described with Verilog☆27Jun 1, 2013Updated 12 years ago
- Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals☆16Jan 11, 2020Updated 6 years ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆20May 30, 2019Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Jul 7, 2016Updated 9 years ago
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- migen + misoc + redpitaya = digital servo☆41Jan 11, 2019Updated 7 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- RCA COSMAC CDP1802 functional equivalent CPU core in VHDL☆27Jan 7, 2018Updated 8 years ago
- Featherweight RISC-V implementation☆53Jan 17, 2022Updated 4 years ago
- experimental drm plugin for SDRuno☆20Jul 6, 2024Updated last year
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆33Jun 30, 2021Updated 4 years ago
- Open Processor Architecture☆26Apr 7, 2016Updated 9 years ago
- SPI ELF bootloader for Xilinx Microblaze processors☆27Oct 17, 2017Updated 8 years ago
- An rtl_tcp compatible IQ server for the RSP range of SDRPlay SDR in combination with websdr.org servers.☆21Dec 29, 2023Updated 2 years ago
- ☆21Apr 16, 2022Updated 3 years ago
- simple commandline jtag stuff☆35May 26, 2018Updated 7 years ago
- ☆11Dec 19, 2016Updated 9 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆43Jan 18, 2024Updated 2 years ago
- Equihash Proof of Work for Node.js☆10Oct 3, 2017Updated 8 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Dec 25, 2022Updated 3 years ago
- OpenTitan: Open source silicon root of trust☆10Feb 5, 2020Updated 6 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago