aswaterman / trainwreck
Original RISC-V 1.0 implementation. Not supported.
☆41Updated 6 years ago
Alternatives and similar repositories for trainwreck:
Users that are interested in trainwreck are comparing it to the libraries listed below
- ☆45Updated 2 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Chisel Cheatsheet☆33Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Platform Level Interrupt Controller☆36Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- The multi-core cluster of a PULP system.☆85Updated last week
- Simple runtime for Pulp platforms☆42Updated this week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- The specification for the FIRRTL language☆51Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated last month
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- This repo includes XiangShan's function units☆18Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- A Rocket-based RISC-V superscalar in-order core☆30Updated this week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆139Updated 3 weeks ago
- ☆82Updated last month
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- Lipsi: Probably the Smallest Processor in the World☆83Updated 11 months ago