A Scalable BFS Accelerator on FPGA-HBM Platform
☆14Feb 22, 2024Updated 2 years ago
Alternatives and similar repositories for ScalaBFS
Users that are interested in ScalaBFS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆26Dec 1, 2020Updated 5 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆119Jun 15, 2025Updated last year
- Blaze: Fast Graph Processing on Fast SSDs (SC'22)☆11Oct 12, 2022Updated 3 years ago
- Source code for XPGraph-MICRO22☆11Apr 10, 2023Updated 3 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆13Apr 15, 2025Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 6 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- ☆15May 23, 2024Updated 2 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆19Dec 11, 2018Updated 7 years ago
- ☆15Jun 14, 2022Updated 4 years ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆19Nov 6, 2025Updated 8 months ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- A Dataflow library for graph analytics acceleration☆14Dec 15, 2015Updated 10 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆193Mar 8, 2026Updated 4 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆21Aug 8, 2022Updated 3 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆16Aug 29, 2021Updated 4 years ago
- ☆19Nov 21, 2022Updated 3 years ago
- ☆14Jan 24, 2023Updated 3 years ago
- Lipsi: Probably the Smallest Processor in the World☆90Apr 15, 2024Updated 2 years ago
- Source code for the paper: Accelerating Dynamic Graph Analytics on GPUs☆30Jun 19, 2023Updated 3 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆24Jun 30, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Starlight: A Kernel Optimizer for GPU Processing☆16Jan 10, 2024Updated 2 years ago
- ☆20Nov 14, 2022Updated 3 years ago
- ☆16Jun 13, 2021Updated 5 years ago
- VNx: Vitis Network Examples☆162Aug 25, 2025Updated 10 months ago
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- PoWx mission: Aiming at smaller energy per hash hardware.☆11Dec 18, 2021Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆22Dec 10, 2018Updated 7 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- CPC2018第二届国产CPU并行应用挑战赛决赛☆11Oct 26, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆38Mar 30, 2022Updated 4 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆15Nov 15, 2022Updated 3 years ago
- Alveo Versal Example Design☆69Jun 11, 2026Updated last month
- ☆30Apr 4, 2024Updated 2 years ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Jul 1, 2026Updated 2 weeks ago
- Vivado board files for the Kintex 7 HPC V2 FPGA board.☆25Jul 31, 2020Updated 5 years ago