umd-memsys / DRAMsim3Links
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
☆411Updated last year
Alternatives and similar repositories for DRAMsim3
Users that are interested in DRAMsim3 are comparing it to the libraries listed below
Sorting:
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆400Updated 2 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆306Updated last week
- BookSim 2.0☆368Updated last year
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆492Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆248Updated 2 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆281Updated 4 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆657Updated 2 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆197Updated 5 years ago
- Network on Chip Simulator☆287Updated 2 months ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆209Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆178Updated this week
- ☆103Updated this week
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆177Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆462Updated 2 months ago
- ☆195Updated 3 months ago
- Modeling Architectural Platform☆206Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆152Updated 7 months ago
- Comment on the rocket-chip source code☆180Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆225Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆210Updated 4 months ago
- RiVEC Bencmark Suite☆123Updated 10 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆282Updated 2 weeks ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- Repository to host and maintain SCALE-Sim code☆349Updated last month
- A scalable High-Level Synthesis framework on MLIR☆278Updated last year
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆122Updated 7 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆189Updated 2 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 3 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 3 months ago