umd-memsys / DRAMsim3
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
☆351Updated 7 months ago
Alternatives and similar repositories for DRAMsim3:
Users that are interested in DRAMsim3 are comparing it to the libraries listed below
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆433Updated 8 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆229Updated 2 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆298Updated 3 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆244Updated 4 months ago
- DRAMSim2: A cycle accurate DRAM simulator☆264Updated 4 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆179Updated 4 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆618Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆405Updated this week
- BookSim 2.0☆308Updated 8 months ago
- Modeling Architectural Platform☆179Updated this week
- Fast and accurate DRAM power and energy estimation tool☆149Updated this week
- ☆124Updated 2 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆183Updated this week
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆193Updated last year
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆154Updated 2 years ago
- Comment on the rocket-chip source code☆174Updated 6 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆190Updated last week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆459Updated last month
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆150Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆273Updated last year
- ☆309Updated 6 months ago
- ☆74Updated this week
- Network on Chip Simulator☆259Updated last year
- ☆158Updated last month
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆360Updated this week
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆152Updated 10 months ago
- Chisel examples and code snippets☆246Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆246Updated last week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆142Updated 2 years ago