Alternatives and similar repositories for DRAMsim3

Users that are interested in DRAMsim3 are comparing it to the libraries listed below

• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆431Updated 3 weeks ago
• booksim / booksim2
  BookSim 2.0
  ☆380Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆317Updated last month
• HewlettPackard / cacti
  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
  ☆508Updated last year
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆251Updated 3 years ago
• CMU-SAFARI / ramulator
  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …
  ☆668Updated 2 years ago
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆291Updated 5 years ago
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆202Updated 5 years ago
• davidepatti / noxim
  Network on Chip Simulator
  ☆291Updated 2 weeks ago
• vineodd / PIMSim
  PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
  ☆211Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆468Updated 3 months ago
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆185Updated last month
• CMU-SAFARI / ramulator-pim
  A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…
  ☆179Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆218Updated last week
• OpenXiangShan / GEM5
  ☆111Updated last week
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆229Updated 2 years ago
• SEAL-UCSB / NVSim
  NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)
  ☆124Updated 7 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆190Updated this week
• sparcians / map
  Modeling Architectural Platform
  ☆212Updated this week
• scalesim-project / SCALE-Sim
  Repository to host and maintain SCALE-Sim code
  ☆372Updated last week
• RV-BOSC / OpenNoC
  ☆204Updated 4 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆282Updated last year
• snipersim / snipersim
  The Sniper Multi-Core Simulator
  ☆159Updated 3 weeks ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆155Updated 9 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆214Updated 5 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆286Updated 2 weeks ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆143Updated this week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆161Updated 2 years ago