Alternatives and similar repositories for DRAMsim3:

Users that are interested in DRAMsim3 are comparing it to the libraries listed below

• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆298Updated 3 months ago
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆264Updated 4 years ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆230Updated 2 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆244Updated 4 months ago
• HewlettPackard / cacti
  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
  ☆433Updated 8 months ago
• CMU-SAFARI / ramulator
  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …
  ☆618Updated last year
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆179Updated 4 years ago
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆150Updated this week
• booksim / booksim2
  BookSim 2.0
  ☆308Updated 8 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆190Updated this week
• vineodd / PIMSim
  PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
  ☆193Updated last year
• RV-BOSC / OpenNoC
  ☆127Updated 2 weeks ago
• CMU-SAFARI / ramulator-pim
  A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…
  ☆154Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆405Updated this week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆174Updated 6 years ago
• OpenXiangShan / GEM5
  ☆74Updated this week
• harvard-acc / ALADDIN
  A pre-RTL, power-performance model for fixed-function accelerators
  ☆173Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆184Updated this week
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 4 months ago
• ucb-bar / berkeley-hardfloat
  ☆310Updated 6 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆113Updated 3 months ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆142Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆246Updated 2 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• davidepatti / noxim
  Network on Chip Simulator
  ☆259Updated last year
• sparcians / map
  Modeling Architectural Platform
  ☆179Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆150Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• vortexgpgpu / vortex_tutorials
  ☆158Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆128Updated last month