Alternatives and similar repositories for DRAMsim3:

Users that are interested in DRAMsim3 are comparing it to the libraries listed below

• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆322Updated 3 weeks ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆258Updated last month
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆232Updated 2 years ago
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆183Updated 4 years ago
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆270Updated 4 years ago
• CMU-SAFARI / ramulator
  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …
  ☆630Updated last year
• HewlettPackard / cacti
  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
  ☆449Updated 9 months ago
• booksim / booksim2
  BookSim 2.0
  ☆323Updated 10 months ago
• CMU-SAFARI / ramulator-pim
  A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…
  ☆159Updated 2 years ago
• OpenXiangShan / GEM5
  ☆80Updated this week
• davidepatti / noxim
  Network on Chip Simulator
  ☆265Updated last year
• vineodd / PIMSim
  PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
  ☆198Updated 2 years ago
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆156Updated this week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆418Updated last month
• CMU-SAFARI / prim-benchmarks
  PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…
  ☆155Updated 11 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• ucb-bar / berkeley-hardfloat
  ☆319Updated 7 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆185Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆163Updated last week
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆159Updated 4 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• RV-BOSC / OpenNoC
  ☆147Updated 2 weeks ago
• scalesim-project / scale-sim-v2
  Repository to host and maintain scale-sim-v2 code
  ☆283Updated last week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆149Updated 2 years ago
• vortexgpgpu / vortex_tutorials
  ☆166Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆194Updated last month
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆250Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆138Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆480Updated 2 months ago