umd-memsys / DRAMsim3Links
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
☆380Updated 11 months ago
Alternatives and similar repositories for DRAMsim3
Users that are interested in DRAMsim3 are comparing it to the libraries listed below
Sorting:
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆357Updated 2 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆287Updated 2 months ago
- BookSim 2.0☆345Updated last year
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆473Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆240Updated 2 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆189Updated 4 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆274Updated 4 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆643Updated last year
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆205Updated 2 years ago
- ☆89Updated this week
- Network on Chip Simulator☆280Updated last year
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆170Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆168Updated last week
- Modeling Architectural Platform☆194Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆204Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆154Updated 2 years ago
- RiVEC Bencmark Suite☆117Updated 7 months ago
- A scalable High-Level Synthesis framework on MLIR☆265Updated last year
- Repository to host and maintain scale-sim-v2 code☆315Updated 2 months ago
- ☆168Updated 3 weeks ago
- The Sniper Multi-Core Simulator☆136Updated 8 months ago
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆159Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆441Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆148Updated 5 months ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆116Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆133Updated 3 weeks ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆184Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆204Updated last month