yuezuegu / sosa-compilerLinks
Repository for compilation and cycle-accurate simulator for scale-out systolic arrays
☆16Updated 2 years ago
Alternatives and similar repositories for sosa-compiler
Users that are interested in sosa-compiler are comparing it to the libraries listed below
Sorting:
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆59Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆30Updated 8 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆54Updated 3 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆25Updated last year
- STONNE: A Simulation Tool for Neural Networks Engines☆133Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- ☆92Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated 11 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆55Updated 3 months ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆37Updated last year
- ☆41Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- MICRO22 artifact evaluation for Sparseloop☆45Updated 2 years ago
- ☆32Updated 3 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆133Updated 5 months ago
- agile hardware-software co-design☆50Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 11 months ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- Heterogenous ML accelerator☆18Updated 2 months ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated 2 weeks ago