scalesim-project / scale-sim-v3Links
☆29Updated 2 months ago
Alternatives and similar repositories for scale-sim-v3
Users that are interested in scale-sim-v3 are comparing it to the libraries listed below
Sorting:
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆85Updated 3 months ago
- A co-design architecture on sparse attention☆51Updated 3 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆17Updated 4 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆45Updated 3 months ago
- ☆49Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- ☆38Updated 2 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆42Updated last year
- ☆47Updated 2 weeks ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆60Updated 7 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆29Updated last year
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆13Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆30Updated 2 weeks ago
- ☆77Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆35Updated 7 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- ☆17Updated 10 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆88Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- ☆68Updated 5 months ago