scalesim-project / scale-sim-v3View external linksLinks
☆57Nov 29, 2025Updated 2 months ago
Alternatives and similar repositories for scale-sim-v3
Users that are interested in scale-sim-v3 are comparing it to the libraries listed below
Sorting:
- The wafer-native AI accelerator simulation platform and inference engine.☆50Jan 1, 2026Updated last month
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Jan 2, 2025Updated last year
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Nebula: Deep Neural Network Benchmarks in C++☆13Jan 2, 2025Updated last year
- Repository to host and maintain SCALE-Sim code☆412Feb 2, 2026Updated last week
- This repository presents the source code for the paper "MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Qu…☆23Apr 2, 2025Updated 10 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆184Jan 8, 2026Updated last month
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Dec 9, 2024Updated last year
- ☆224Oct 24, 2025Updated 3 months ago
- ☆12Apr 15, 2025Updated 9 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Mar 29, 2025Updated 10 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆108Apr 28, 2025Updated 9 months ago
- LLMServingSim: A HW/SW Co-Simulation Infrastructure for LLM Inference Serving at Scale☆178Jul 18, 2025Updated 6 months ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 2 months ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 5 months ago
- ☆11Jul 2, 2024Updated last year
- ☆13Jul 25, 2024Updated last year
- ☆27Aug 4, 2025Updated 6 months ago
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm☆16Oct 11, 2020Updated 5 years ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆16Nov 6, 2025Updated 3 months ago
- GPU-accelerated LLM Training Simulator☆17Jun 26, 2025Updated 7 months ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Dec 6, 2020Updated 5 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- Enhance CHISEL for Smooth and Comfortable Chip Design☆19Feb 1, 2026Updated 2 weeks ago
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆90Updated this week
- [ICML 2021] "Double-Win Quant: Aggressively Winning Robustness of Quantized DeepNeural Networks via Random Precision Training and Inferen…☆16Feb 13, 2022Updated 4 years ago
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Dec 18, 2023Updated 2 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆37Aug 9, 2025Updated 6 months ago
- ☆35Jul 9, 2020Updated 5 years ago
- ☆42Mar 31, 2025Updated 10 months ago
- ☆17Mar 26, 2025Updated 10 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆87Apr 26, 2025Updated 9 months ago
- WaferLLM: Large Language Model Inference at Wafer Scale☆88Jan 7, 2026Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆71Dec 29, 2025Updated last month
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆122Aug 27, 2024Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆163Updated this week