DfX-NYUAD / GNN4IC
Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of papers is summarized in the following survey paper; L. Alrahis et al. "Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs," ASP-DAC, 2023.
☆39Updated last year
Related projects ⓘ
Alternatives and complementary repositories for GNN4IC
- GNN-RE datasets for circuit recognition☆38Updated last year
- ☆14Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆63Updated 2 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆113Updated last month
- just checking☆13Updated 2 years ago
- Artificial Netlist Generator☆32Updated 7 months ago
- ☆15Updated 3 years ago
- Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 2022☆18Updated last year
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆58Updated 2 weeks ago
- ☆27Updated 11 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆19Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆47Updated this week
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆45Updated 5 months ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆18Updated 2 years ago
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆127Updated 4 months ago
- ☆12Updated 5 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆35Updated last month
- ☆20Updated 6 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year
- Analog Placement Quality Prediction☆19Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆26Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆75Updated last week
- Open Circuit Benchmark OCB and source code for CktGNN (https://openreview.net/forum?id=NE2911Kq1sp).☆44Updated last year
- ☆49Updated 3 years ago
- Collection of digital hardware modules & projects (benchmarks)☆31Updated last week
- ☆11Updated last year
- Approximation-Aware Functional Reverse Engineering using Graph Neural Networks☆9Updated 2 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆19Updated 2 months ago
- ☆71Updated 3 weeks ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆17Updated 4 months ago