Alternatives and similar repositories for mvsis

Users that are interested in mvsis are comparing it to the libraries listed below

• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆11Updated last year
• RohanNagar / parallel-logic-networks
  Gate-Level Simulation on a GPU
  ☆10Updated 8 years ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago
• lsils / kitty
  C++ truth table library
  ☆57Updated 2 months ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 3 weeks ago
• lsils / bill
  C++ header-only reasoning library
  ☆16Updated last year
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆23Updated 3 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• cucapra / patronus
  work in progress, playing around with btor2 in rust
  ☆11Updated 3 weeks ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆17Updated 6 years ago
• gussmith23 / churchroad
  FPGA synthesis tool powered by equality saturation and program synthesis.
  ☆12Updated last week
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆13Updated 4 years ago
• stdgregwar / elve
  ELVE : ELVE Logic Visualization Engine
  ☆11Updated 8 years ago
• mgudemann / iimc
  ☆13Updated 7 years ago
• SamuelBayliss / Potholes
  Polyhedral Compilation tool for High Level Synthesis.
  ☆10Updated 11 years ago
• chengyinwu / V3
  An Extensible Framework for Hardware Verification and Debugging
  ☆18Updated 2 years ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 2 weeks ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 6 years ago
• opencomputeproject / ODSA-CDXML
  TBD
  ☆12Updated 5 months ago
• michalpaszkowski / LLVM-Canon
  LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…
  ☆15Updated last year
• eytans / easter-egg
  easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once
  ☆13Updated 3 months ago
• ics-jku / epex-formal-rv32-model
  A RISC-V RV32 model ready for SMT program synthesis.
  ☆11Updated 4 years ago
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 2 weeks ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• iscas-tis / CHA
  ☆19Updated last year
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 months ago