skycrapers / Eva-CiMLinks
Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020
☆11Updated 4 years ago
Alternatives and similar repositories for Eva-CiM
Users that are interested in Eva-CiM are comparing it to the libraries listed below
Sorting:
- ☆18Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆73Updated 5 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆29Updated last year
- a Computing In Memory emULATOR framework☆14Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆59Updated last week
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆23Updated 3 years ago
- ☆17Updated 3 months ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆11Updated 2 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Updated last year
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆160Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆52Updated 4 years ago
- A list of our chiplet simulaters☆35Updated 2 months ago
- ☆27Updated last year
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated last year
- C++ code for HLS FPGA implementation of transformer☆17Updated 11 months ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆43Updated 5 years ago
- ☆31Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems☆171Updated 9 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Collection of kernel accelerators optimised for LLM execution☆19Updated 4 months ago
- ☆11Updated last year
- Processing in Memory Emulation☆21Updated 2 years ago
- ☆70Updated 6 months ago