☆14Oct 11, 2024Updated last year
Alternatives and similar repositories for ChipletDesignFlow
Users that are interested in ChipletDesignFlow are comparing it to the libraries listed below
Sorting:
- Source code for Multifidielity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures☆21Jan 29, 2026Updated last month
- This GitHub repo contains the artifact for CPElide, which appears at MICRO '24☆15Sep 7, 2024Updated last year
- Problem B: 3D Placement with D2D Vertical Connections☆11Jun 30, 2022Updated 3 years ago
- ☆24Aug 11, 2020Updated 5 years ago
- ☆10Mar 28, 2025Updated 11 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 2 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆75Jul 25, 2025Updated 7 months ago
- A collection of papers in the area of photonic design automation☆81Feb 7, 2024Updated 2 years ago
- ☆13Jul 25, 2024Updated last year
- ☆33Dec 11, 2025Updated 3 months ago
- ☆16Mar 18, 2025Updated last year
- ☆23Oct 7, 2025Updated 5 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Jul 29, 2020Updated 5 years ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- ☆22Nov 3, 2025Updated 4 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆75Jun 30, 2024Updated last year
- ☆14Aug 17, 2024Updated last year
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆27Dec 18, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆87Jan 4, 2026Updated 2 months ago
- BBO optimiser☆11Feb 11, 2020Updated 6 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆64Mar 17, 2025Updated last year
- Medusa Repository: Transynther tool and Medusa Attack☆23Jul 17, 2020Updated 5 years ago
- ☆30Jul 12, 2025Updated 8 months ago
- [ASICON'25] User-friendly lithography simulation engine for full-chip scale mask optimization☆41Dec 17, 2025Updated 3 months ago
- This project is a open-source yield analysis for SRAM circuits☆20Mar 13, 2026Updated last week
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- A Parallel Simulation Framework For Multicore Systems☆10May 20, 2017Updated 8 years ago
- ☆12Jan 13, 2023Updated 3 years ago
- ☆29Aug 4, 2025Updated 7 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- A list of our chiplet simulaters☆48Jun 22, 2025Updated 8 months ago
- Tensorflow implementation of "Defense against Universal Adversarial Perturbations"☆10Apr 16, 2018Updated 7 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- VLSI placement and routing tool☆15Dec 20, 2025Updated 3 months ago
- A Multi-objective Multi-fidelity acquisition function for Bayesian optimization based on EHVI method.☆14May 18, 2022Updated 3 years ago
- A benchmark suite for Graph Machine Learning☆19Oct 8, 2024Updated last year