shahsaumya00 / D-Algorithm-CombinationalLinks
Combinational ATPG generator based on D-Algorithm
☆16Updated 4 years ago
Alternatives and similar repositories for D-Algorithm-Combinational
Users that are interested in D-Algorithm-Combinational are comparing it to the libraries listed below
Sorting:
- A Standalone Structural Verilog Parser☆97Updated 3 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆96Updated 3 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆189Updated 5 years ago
- ☆201Updated 7 months ago
- Introductory course into static timing analysis (STA).☆98Updated 3 months ago
- Logic synthesis and ABC based optimization☆50Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆268Updated this week
- Physical Design Flow from RTL to GDS using Opensource tools.☆111Updated 4 years ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆82Updated last year
- ☆177Updated 4 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- EDA wiki☆132Updated 6 months ago
- IDEA project source files☆108Updated 2 months ago
- ☆44Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- ☆89Updated this week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆100Updated 3 years ago
- SAT-based ATPG using TG-Pro model☆17Updated 7 years ago
- ☆31Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆34Updated 3 months ago
- ☆44Updated 3 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆185Updated 4 months ago
- Some useful documents of Synopsys☆88Updated 3 years ago