Alternatives and similar repositories for KicadParser:

Users that are interested in KicadParser are comparing it to the libraries listed below

• The-OpenROAD-Project / PcbRouter
  ☆29Updated 4 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 5 years ago
• The-OpenROAD-Project / PCB-PR-App
  ☆15Updated 4 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆12Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• The-OpenROAD-Project / SA-PCB
  Annealing-based PCB placement tool
  ☆37Updated 4 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• digaryfa / UTH-Timer
  Gate-level timing estimation toolkit
  ☆22Updated 3 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆19Updated 4 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆55Updated 2 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆85Updated 4 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆57Updated 10 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• aolofsson / IDEA
  ☆34Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• The-OpenROAD-Project-Attic / Resizer
  ☆14Updated 5 years ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆9Updated 8 years ago
• The-OpenROAD-Project-Attic / lef
  Si2 LEF parser
  ☆9Updated 4 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆17Updated 2 years ago
• ckchengucsd / ILP-SAT-Detailed-Router
  ILP SAT Detailed Router
  ☆11Updated 5 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆36Updated 9 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 2 weeks ago