Alternatives and similar repositories for KicadParser

Users that are interested in KicadParser are comparing it to the libraries listed below

• The-OpenROAD-Project / PCB-PR-App
  ☆17Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 5 years ago
• The-OpenROAD-Project / PcbRouter
  ☆34Updated 5 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆12Updated 5 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆13Updated 6 years ago
• The-OpenROAD-Project / SA-PCB
  Annealing-based PCB placement tool
  ☆39Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆94Updated 4 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆24Updated 5 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆33Updated 5 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆120Updated 4 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆19Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 5 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆133Updated last year
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆187Updated 6 months ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆140Updated 2 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆58Updated 3 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆140Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆107Updated last year
• The-OpenROAD-Project / OpeNPDN
  Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.
  ☆34Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 weeks ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• digaryfa / UTH-Timer
  Gate-level timing estimation toolkit
  ☆25Updated 3 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆77Updated 7 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆58Updated last year
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆18Updated 3 years ago