RoaLogic / vga_lcdLinks
VGA LCD Core (OpenCores)
☆15Updated 7 years ago
Alternatives and similar repositories for vga_lcd
Users that are interested in vga_lcd are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated last week
- ☆60Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 10 months ago
- Open Source PHY v2☆33Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- ☆38Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆31Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Wishbone interconnect utilities☆44Updated last month
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Updated 7 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- RISC-V Nox core☆71Updated 6 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- An open source PDK using TIGFET 10nm devices.☆56Updated 3 years ago
- ☆33Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated last week
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago