RoaLogic / vga_lcdLinks
VGA LCD Core (OpenCores)
☆15Updated 7 years ago
Alternatives and similar repositories for vga_lcd
Users that are interested in vga_lcd are comparing it to the libraries listed below
Sorting:
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆30Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- ☆60Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- A padring generator for ASICs☆25Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 9 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Wishbone interconnect utilities☆44Updated 2 weeks ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ☆33Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆55Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- ☆18Updated 5 years ago
- SAR ADC on tiny tapeout☆44Updated 11 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆32Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week