symmetric clock tree synthesis for NTV IC design
☆11May 8, 2022Updated 3 years ago
Alternatives and similar repositories for Sym-CTS
Users that are interested in Sym-CTS are comparing it to the libraries listed below
Sorting:
- Technology file parser in Rust☆13Apr 6, 2021Updated 4 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆34Aug 4, 2023Updated 2 years ago
- A LEF/DEF Utility.☆33Aug 15, 2019Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- ☆10Aug 12, 2021Updated 4 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 10 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- ☆16Apr 23, 2018Updated 7 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- General purpose task runner☆10Nov 10, 2025Updated 3 months ago
- Implementation of several grid routers in Rust☆13Updated this week
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Inserting elements into this map yields a persistent, type-safe Index to that new element.☆13Oct 15, 2018Updated 7 years ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- My git repository of minigui - MiniGUI - a compact cross-OS Graphics User Interface support system for real-time embedded systems.☆20Oct 11, 2009Updated 16 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆15Feb 17, 2019Updated 7 years ago
- ☆15May 8, 2018Updated 7 years ago
- All the stuffs related to miui porting device Google Nexus 5☆10Mar 10, 2016Updated 9 years ago
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆17Oct 4, 2022Updated 3 years ago
- Open source EDA chip design flow☆51Mar 15, 2017Updated 8 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆64Jan 13, 2025Updated last year
- Converts GDSII (IC layout database) files to SVG (Vector graphics) files.☆13Feb 10, 2023Updated 3 years ago
- 一生一芯RISCV处理器核代码仓库（包括相关工具）☆15Sep 11, 2024Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Research compiler based on algorithmic skeletons☆23Oct 18, 2014Updated 11 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆23Feb 24, 2026Updated last week
- This repository contains code to perform conformal mapping of a given 3D mesh onto a sphere using tuette energy minimization and harmonic…☆14Dec 29, 2017Updated 8 years ago
- ☆15Apr 30, 2021Updated 4 years ago
- Json Signing, Verification☆19Jul 16, 2023Updated 2 years ago
- A simple blog for documenting my thoughts and adventures☆18Jul 28, 2025Updated 7 months ago
- A Python library that reads LEF and DEF files, extract the RC parasitics and generate their corresponding SPEF file.☆17Sep 23, 2020Updated 5 years ago
- PROTON - A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids☆18Sep 10, 2024Updated last year
- Bounded-Skew DME v1.3☆15Aug 3, 2018Updated 7 years ago
- digital logic sim☆18Aug 1, 2022Updated 3 years ago
- Currently only a playground for rust, wgpu, openlayers web mapping combo☆19Feb 18, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Feb 22, 2026Updated last week