circuitgraph / logiclockingLinks
Lock circuitgraphs using various logic locking techniques
☆10Updated 2 years ago
Alternatives and similar repositories for logiclocking
Users that are interested in logiclocking are comparing it to the libraries listed below
Sorting:
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- ☆234Updated 10 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆201Updated 5 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆67Updated 8 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆57Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆30Updated 6 years ago
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- A complete open-source design-for-testing (DFT) Solution☆179Updated 5 months ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆87Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- Tools for working with circuits as graphs in python☆126Updated 2 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆107Updated 7 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆280Updated last month
- A logic synthesis tool☆84Updated 4 months ago
- ☆189Updated 4 years ago
- EPFL logic synthesis benchmarks☆227Updated 2 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- Artificial Netlist Generator☆46Updated last year
- Machine Generated Analog IC Layout☆267Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆120Updated 5 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- This is a probabilistic SAT attack tool.☆14Updated 4 years ago
- IDEA project source files☆111Updated 3 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆202Updated 3 weeks ago
- ☆160Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Updated 4 years ago