Alternatives and similar repositories for cpu_gs132:

Users that are interested in cpu_gs132 are comparing it to the libraries listed below

• himanshu5-prog / vortexGPU
  ☆19Updated 3 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆15Updated 2 years ago
• Icenowy / ice-risc
  RISC CPU by Icenowy
  ☆12Updated 6 years ago
• b-dmitry1 / V188
  FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
  ☆21Updated 3 years ago
• kontais / EFI-MIPS
  UEFI, on Loongson.
  ☆14Updated 8 years ago
• zenonxiu81 / arm_system_register_parser
  A python parser for decoding arm aarch32 and aarch64 system registers
  ☆15Updated last year
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆35Updated 9 months ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 5 years ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 5 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆25Updated 3 months ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆18Updated 3 weeks ago
• loongson-community / docs
  Collection of Loongson products' public documentation
  ☆68Updated last week
• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆12Updated 4 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆23Updated 3 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 8 months ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 4 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• intel / MultiArchUefiPkg
  Multi-Architecture UEFI Environment Driver
  ☆56Updated last month
• loongson / la-asm-manual
  ☆16Updated 2 months ago
• freecores / amber
  Amber ARM-compatible core
  ☆11Updated 10 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆49Updated 6 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 2 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆47Updated 3 years ago
• loongson-community / grub
  GRUB source tree for Loongson (MIPS64-EFI)
  ☆16Updated 3 years ago
• RSPwFPGAs / virtio-fpga-bridge
  Virtio front-end and back-end bridge, implemented with FPGA.
  ☆28Updated 4 years ago
• riscvarchive / riscv-edk2
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆23Updated 3 years ago
• jiegec / la-inst
  Examine and discover LoongArch instructions
  ☆14Updated last year