Alternatives and similar repositories for cpu_gs132:

Users that are interested in cpu_gs132 are comparing it to the libraries listed below

• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 5 years ago
• Icenowy / ice-risc
  RISC CPU by Icenowy
  ☆12Updated 6 years ago
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆36Updated 10 months ago
• kontais / EFI-MIPS
  UEFI, on Loongson.
  ☆14Updated 8 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆48Updated 3 years ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 5 years ago
• dtcxzyw / static-key
  Header-only C/C++ static keys to avoid the overhead of conditional branches
  ☆12Updated last year
• riscvarchive / riscv-edk2
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆24Updated 3 years ago
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆15Updated 2 years ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• himanshu5-prog / vortexGPU
  ☆20Updated 3 years ago
• OpenXiangShan / nexus-am
  ☆33Updated last week
• zenonxiu81 / arm_system_register_parser
  A python parser for decoding arm aarch32 and aarch64 system registers
  ☆15Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated last week
• intel / MultiArchUefiPkg
  Multi-Architecture UEFI Environment Driver
  ☆56Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• ashwio / arm64-sysreg-lib
  Header-only C library for reading/writing 64-bit Arm registers, automatically generated by parsing the AArch64 System Register XML.
  ☆30Updated 3 years ago
• riscv-non-isa / riscv-uefi
  ☆29Updated 2 years ago
• loongson-community / grub
  GRUB source tree for Loongson (MIPS64-EFI)
  ☆16Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 3 years ago
• michaeljclark / musl-riscv-toolchain
  riscv-linux musl gcc toolchain bootstrap scripts
  ☆17Updated 4 years ago
• loongson-community / docs
  Collection of Loongson products' public documentation
  ☆69Updated 3 weeks ago
• b-dmitry1 / V188
  FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
  ☆21Updated 3 years ago
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆37Updated this week
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆12Updated 5 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 9 months ago