Alternatives and similar repositories for cpu_gs132

Users that are interested in cpu_gs132 are comparing it to the libraries listed below

• Icenowy / ice-risc
  RISC CPU by Icenowy
  ☆12Updated 6 years ago
• loongson-community / docs
  Collection of Loongson products' public documentation
  ☆79Updated last month
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last month
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆52Updated 4 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 7 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• revyos / xuantie-c900-bugs
  Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
  ☆24Updated 2 months ago
• chinchilla222 / nezha-d1
  build mainline SBI and Linux for allwinner D1 nezha board
  ☆10Updated 4 years ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆28Updated 7 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated 2 years ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 6 years ago
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆23Updated 2 years ago
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆41Updated last year
• himanshu5-prog / vortexGPU
  ☆22Updated 4 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆90Updated 4 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆100Updated 3 years ago
• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆60Updated last month
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• dtcxzyw / static-key
  Header-only C/C++ static keys to avoid the overhead of conditional branches
  ☆14Updated last year
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆57Updated 2 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• intel / MultiArchUefiPkg
  Multi-Architecture UEFI Environment Driver
  ☆59Updated 6 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆34Updated 2 years ago