FlyGoat / cpu_gs132Links
Verilog code of Loongson's GS132 core
☆12Updated 5 years ago
Alternatives and similar repositories for cpu_gs132
Users that are interested in cpu_gs132 are comparing it to the libraries listed below
Sorting:
- RISC CPU by Icenowy☆12Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 6 years ago
- Wrappers for open source FPU hardware implementations.☆35Updated last year
- A extremely size-optimized RV32I soft processor for FPGA.☆28Updated 7 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated 2 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 8 months ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- ☆39Updated last week
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year
- OpenSPARC-based SoC☆72Updated 11 years ago
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- Chisel NVMe controller☆24Updated 2 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆25Updated 4 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Updated last year
- Hardware design with Chisel☆35Updated 2 years ago
- RISC-V Online Help☆35Updated 3 months ago
- RV32I by cats☆15Updated 2 years ago
- ☆22Updated 4 years ago
- The 'missing header' for Chisel☆21Updated 7 months ago
- Zet - The x86 (IA-32) open implementation☆22Updated 11 years ago
- ☆61Updated 4 years ago
- RISC-V Online Assembler using Emscripten, Gnu Binutils☆58Updated 2 years ago