Jeremy2001-chen / OS-RISCV
A small RISC-V kernel coding by C, tested on sifive unmatched board.
☆16Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for OS-RISCV
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆14Updated 3 months ago
- C Abstract Machine Interpreter☆10Updated 2 weeks ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆37Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆24Updated 3 months ago
- Recommended coding standard of Verilog and SystemVerilog.☆33Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆69Updated last year
- An emulator to run mips executable and to differentially validate noop.☆7Updated 2 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆35Updated 2 years ago
- Introduction to Computer Systems (II), Spring 2021☆48Updated 3 years ago
- uCore MIPS32 porting☆18Updated 4 years ago
- ☆31Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆16Updated 2 years ago
- Yet another toy CPU.☆84Updated 11 months ago
- ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.☆25Updated last year
- CQU Dual Issue Machine☆34Updated 4 months ago
- A Flexible Cache Architectural Simulator☆11Updated 2 weeks ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆55Updated 2 years ago
- ☆33Updated 5 years ago
- A fast compiler for SysY code☆18Updated 2 years ago
- ☆10Updated 3 months ago
- ☆17Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- A toy compiler for miniSysY, implemented in Rust. (Reference implementation for BUAA-SE-Compiler course project)☆28Updated last year
- The decoder library for jemu execution and web documentation☆55Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆9Updated 2 years ago
- Implements kernels with RISC-V Vector☆21Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆107Updated 3 weeks ago
- ☆21Updated last year