A small RISC-V kernel coding by C, tested on sifive unmatched board.
☆16Aug 20, 2022Updated 3 years ago
Alternatives and similar repositories for OS-RISCV
Users that are interested in OS-RISCV are comparing it to the libraries listed below
Sorting:
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10May 15, 2021Updated 4 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Aug 9, 2024Updated last year
- My blog☆11Jul 6, 2025Updated 7 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Aug 29, 2023Updated 2 years ago
- 2022华为毕昇杯-喵喵队仰卧起坐-参赛作品☆17Dec 25, 2022Updated 3 years ago
- 北京航空航天大学 BUAA LaTeX Beamer 非官方主题☆36Mar 31, 2025Updated 11 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Jul 25, 2024Updated last year
- MIPS OS on R3000 (course assignment for BUAA-Operating-System)☆22Mar 16, 2022Updated 3 years ago
- 龙芯杯21个人赛作品☆36Sep 15, 2021Updated 4 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Jan 26, 2022Updated 4 years ago
- Project for 2021-autumn Compiler course in BUAA-SCSE.☆32Dec 30, 2021Updated 4 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated last year
- Generic C-like Preprocessor for Rust☆13Jun 27, 2023Updated 2 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- ☆15Feb 5, 2026Updated 3 weeks ago
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- BUAA OS Lab "MOS" Open Source Repository | 北航操作系统课程 MOS 内核实验开源代码仓库☆30May 2, 2025Updated 9 months ago
- a compiler for CSC-Compiler-2022☆13Aug 22, 2022Updated 3 years ago
- ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.☆28Jun 25, 2023Updated 2 years ago
- 2022全国大学生计算机系统能力大赛 - 操作系统赛 - 内核实现赛道 作品☆16Apr 9, 2024Updated last year
- rewrite subset of linux 2.6 by OOP, C++ advanced topics☆10Jul 22, 2021Updated 4 years ago
- My tests and experiments with some popular dl frameworks.☆17Sep 11, 2025Updated 5 months ago
- Environment control for benchmarks☆14Feb 10, 2025Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆18May 15, 2022Updated 3 years ago
- Embedded system single board system performance benchmarks☆15Jan 4, 2021Updated 5 years ago
- 北航计算机专业课 代码及期末复习笔记☆19Apr 10, 2022Updated 3 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆94Oct 17, 2025Updated 4 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Oct 31, 2024Updated last year
- ☆16Jul 31, 2024Updated last year
- A Verilog module for disassembling MIPS code.☆16Dec 10, 2022Updated 3 years ago
- User programs for rCore OS☆19Jun 7, 2022Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Jul 4, 2023Updated 2 years ago
- A fork of Xiangshan for AI☆36Feb 6, 2026Updated 3 weeks ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- My resume☆65Jan 9, 2026Updated last month
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Dec 18, 2025Updated 2 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 2 months ago