Alternatives and similar repositories for OS-RISCV

Users that are interested in OS-RISCV are comparing it to the libraries listed below

• t123yh / MIPSCPU
  A simple MIPS CPU for BUAA CO course (and now NSCSCC).
  ☆10Updated 4 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 4 years ago
• Jrinx / Jrinx
  ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.
  ☆29Updated 2 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆32Updated last year
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆13Updated last year
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆76Updated 2 weeks ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆22Updated 8 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆16Updated 4 months ago
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆36Updated last week
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• iFuProcessor / iFuCore
  ☆20Updated last year
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆51Updated last month
• yu-yake2002 / ysyx-docker
  A docker image for One Student One Chip's debug exam
  ☆10Updated 2 years ago
• hanhwi / SimPoint
  ☆17Updated 3 years ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• miaochenlu / Gem5_tutorials
  ☆22Updated 2 months ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆92Updated 2 years ago
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆17Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated 3 weeks ago
• HeliosXCore / HeliosXCore
  HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.
  ☆10Updated last year
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago