pkorolov / zynq-fpga
RISC-V Rocket on the Digilent Zybo Board
☆21Updated 10 years ago
Alternatives and similar repositories for zynq-fpga:
Users that are interested in zynq-fpga are comparing it to the libraries listed below
- RISC-V RV32IMAFC Core for MCU☆36Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- ☆27Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 5 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 5 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆100Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆83Updated last week
- ☆53Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- ☆21Updated 5 years ago
- A demo system for Ibex including debug support and some peripherals☆62Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago