jiegec / chisel-memory-lowerLinks
Lower chisel memories to SRAM macros
☆12Updated last year
Alternatives and similar repositories for chisel-memory-lower
Users that are interested in chisel-memory-lower are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- ☆17Updated 8 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 11 months ago
- Run Rocket Chip on VCU128☆30Updated 2 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Updated 2 years ago
- ☆22Updated last month
- Wrappers for open source FPU hardware implementations.☆35Updated 3 weeks ago
- ☆52Updated 11 months ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆38Updated 2 months ago
- Asynchronous semantics for architectural simulation and synthesis.☆60Updated last week
- BOOM's Simulation Accelerator.☆13Updated 4 years ago
- A router IP written in Verilog.☆12Updated 6 years ago
- ☆17Updated 3 years ago
- What if everything is a io_uring?☆16Updated 3 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆78Updated 2 months ago
- Microarchitecture diagrams of several CPUs☆44Updated this week
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- CQU Dual Issue Machine☆38Updated last year
- ☆15Updated 3 years ago
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10Updated 4 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- ☆35Updated 4 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- My RV64 CPU (Work in progress)☆19Updated 3 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated 6 months ago