jiegec / chisel-memory-lowerLinks
Lower chisel memories to SRAM macros
☆12Updated last year
Alternatives and similar repositories for chisel-memory-lower
Users that are interested in chisel-memory-lower are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 2 weeks ago
- ☆17Updated 6 months ago
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Microarchitecture diagrams of several CPUs☆43Updated last week
- ☆17Updated 3 years ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆12Updated 2 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆30Updated 9 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆23Updated last year
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆73Updated last week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆41Updated 4 months ago
- ☆47Updated 9 months ago
- CQU Dual Issue Machine☆37Updated last year
- A router IP written in Verilog.☆12Updated 5 years ago
- ☆20Updated 4 months ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆38Updated 2 weeks ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆14Updated 4 months ago
- Asynchronous semantics for architectural simulation and synthesis.☆53Updated this week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆31Updated 2 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated 11 months ago
- BOOM's Simulation Accelerator.☆14Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 2 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- Running ahead of memory latency - Part II project☆10Updated 2 years ago