Alternatives and similar repositories for chisel-memory-lower

Users that are interested in chisel-memory-lower are comparing it to the libraries listed below

• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆34Updated 11 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated 3 weeks ago
• pku-liang / ksim
  ☆52Updated 11 months ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• pku-liang / Hestia
  ☆17Updated 8 months ago
• fpgasystems / hacc
  ETHZ Heterogeneous Accelerated Compute Cluster.
  ☆38Updated 2 months ago
• miaochenlu / Gem5_tutorials
  ☆22Updated last month
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆12Updated 6 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• Synthesys-Lab / assassyn
  Asynchronous semantics for architectural simulation and synthesis.
  ☆60Updated last week
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆44Updated last week
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆19Updated last year
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆13Updated 4 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆24Updated 3 weeks ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…
  ☆78Updated 2 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 3 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• WukLab / FPGA-OS
  ☆35Updated 4 years ago
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆33Updated 4 months ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• t123yh / MIPSCPU
  A simple MIPS CPU for BUAA CO course (and now NSCSCC).
  ☆10Updated 4 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago