jiegec / chisel-memory-lower

Related projects ⓘ

Alternatives and complementary repositories for chisel-memory-lower

• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆16Updated this week
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆11Updated this week
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated 10 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 4 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆54Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆19Updated 10 months ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆18Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆16Updated this week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆33Updated this week
• jiegec / kb
  My knowledge base
  ☆38Updated last week
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆24Updated this week
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆16Updated last month
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆17Updated 2 weeks ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated last year
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆31Updated last year
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Updated last year
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆18Updated 2 years ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆10Updated 5 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆21Updated 8 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago