theuppercaseguy / FYP--Risc-V-32-bit-Matrix-MacLinks
A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations
☆10Updated last year
Alternatives and similar repositories for FYP--Risc-V-32-bit-Matrix-Mac
Users that are interested in FYP--Risc-V-32-bit-Matrix-Mac are comparing it to the libraries listed below
Sorting:
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆16Updated 4 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆15Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆11Updated last year
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆16Updated 4 years ago
- M-extension for RISC-V cores.☆31Updated 7 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- RADIX-4 SRT division☆11Updated 5 years ago
- APB Logic☆19Updated 7 months ago
- FIR implemention with Verilog☆48Updated 6 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated this week
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- RISCV CPU implementation in SystemVerilog☆27Updated 9 months ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 6 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- YSYX RISC-V Project NJU Study Group☆16Updated 6 months ago
- Digital IC design and vlsi notes☆12Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- Hardware Formal Verification☆15Updated 4 years ago
- Theia: ray graphic processing unit☆20Updated 11 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- NoC based MPSoC☆11Updated 11 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month