agile-hw / labs
Lab assignments for the Agile Hardware Design course
☆14Updated 11 months ago
Alternatives and similar repositories for labs:
Users that are interested in labs are comparing it to the libraries listed below
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 8 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated last week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated 10 months ago
- ☆91Updated last year
- A Toy-Purpose TPU Simulator☆14Updated 8 months ago
- ☆39Updated last month
- CGRA framework with vectorization support.☆25Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆79Updated 3 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Gem5 with PCI Express integrated.☆16Updated 6 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆28Updated 2 months ago
- ☆28Updated 5 months ago
- RISC-V SST CPU Component☆21Updated 3 weeks ago
- ☆11Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆60Updated this week
- ☆24Updated last year
- ☆22Updated 3 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆87Updated 11 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 11 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 4 months ago
- ☆18Updated last year