Alternatives and similar repositories for labs

Users that are interested in labs are comparing it to the libraries listed below

• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆24Updated 3 weeks ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆46Updated 6 months ago
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆23Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆108Updated last year
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆43Updated 6 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated this week
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆40Updated last week
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated 2 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆123Updated 2 months ago
• tactcomplabs / rev
  RISC-V SST CPU Component
  ☆24Updated 3 months ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆62Updated 7 months ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆45Updated 11 months ago
• yousei-github / ChampSim-Ramulator
  A simulator integrates ChampSim and Ramulator.
  ☆19Updated 4 months ago
• pku-liang / ksim
  ☆52Updated 11 months ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆19Updated last year
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆23Updated last year
• suchandler96 / gem5-NVDLA
  ☆40Updated 8 months ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated this week
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• PrincetonUniversity / Duet
  ☆14Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆61Updated 4 years ago
• ueqri / vis4mesh
  Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
  ☆17Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 3 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• CSA-infra / RISCV-Scalable-Simulation-tutorial
  ☆14Updated 7 months ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 11 years ago