SwarmArch / sim

Related projects: ⓘ

• PolyArch / gem-forge-framework
  ☆21Updated 11 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆30Updated 6 months ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆15Updated 5 months ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆41Updated 3 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆20Updated last year
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆20Updated 6 years ago
• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆28Updated 3 months ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆45Updated 2 years ago
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆45Updated 4 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆83Updated 7 months ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆41Updated 7 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆19Updated 3 years ago
• tactcomplabs / gc64-hmcsim
  Hybrid Memory Cube Simulation & Research Infrastructure
  ☆14Updated 8 months ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆26Updated last year
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆14Updated 3 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆42Updated 2 years ago
• SwarmArch / chronos
  The Chronos FPGA Framework to accelerate ordered applications
  ☆19Updated 4 years ago
• Errare-humanum-est / ProtoGen
  Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…
  ☆15Updated 2 years ago
• pku-liang / ksim
  ☆30Updated 5 months ago
• suchandler96 / gem5-NVDLA
  ☆21Updated 5 months ago
• darchr / parsec-benchmark
  ☆15Updated 3 years ago
• PKUZHOU / GNNear-PACT-2022
  GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing
  ☆11Updated 2 years ago
• gem5-hpca-2023 / gem5-tutorial-codespace
  ☆19Updated last year
• Systems-ShiftLab / PIMProf
  ☆9Updated 2 years ago
• sfu-arch / X-Cache
  ☆13Updated 2 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆26Updated 11 months ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆28Updated 2 years ago
• lizardll / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆13Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆62Updated 5 years ago