Alternatives and similar repositories for riscv-landscape

Users that are interested in riscv-landscape are comparing it to the libraries listed below

• riscv-non-isa / riscv-brs
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆54Updated this week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated 11 months ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆45Updated 3 weeks ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last month
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆54Updated 2 weeks ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆13Updated last year
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated last year
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated 7 months ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆86Updated last year
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• riscv-non-isa / riscv-external-debug-security
  The RISC-V External Debug Security Specification
  ☆20Updated this week
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆61Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆79Updated 6 months ago
• riscv / riscv-aia
  ☆96Updated last month
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆82Updated last week
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆51Updated 4 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated this week
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated 2 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆53Updated 9 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 3 weeks ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆14Updated 6 months ago
• AlSaqr-platform / he-soc
  ☆32Updated last week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 3 weeks ago