Alternatives and similar repositories for riscv-landscape

Users that are interested in riscv-landscape are comparing it to the libraries listed below

• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated 2 months ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆54Updated last month
• riscv-non-isa / riscv-external-debug-security
  The RISC-V External Debug Security Specification
  ☆20Updated this week
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 4 years ago
• riscv-non-isa / riscv-brs
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆55Updated this week
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated 8 months ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 7 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆46Updated 2 weeks ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆80Updated 7 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated 2 weeks ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated last year
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆15Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆78Updated this week
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• riscv-non-isa / riscv-uefi
  ☆34Updated 3 years ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆86Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated 2 weeks ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 8 months ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated 2 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆26Updated 2 years ago
• riscv / riscv-aia
  ☆96Updated 2 months ago
• AlSaqr-platform / he-soc
  ☆32Updated 3 weeks ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆99Updated 6 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆55Updated 10 months ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆64Updated 6 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆33Updated last week