Alternatives and similar repositories for riscv-dejagnu:

Users that are interested in riscv-dejagnu are comparing it to the libraries listed below

• riscv / riscv-test-env
  ☆45Updated 3 months ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• riscvarchive / riscv-strace
  RISC-V strace port
  ☆13Updated 8 years ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• riscvarchive / riscv-4th-workshop-tutorials
  4th RISC-V Workshop Tutorials
  ☆15Updated 8 years ago
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆26Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated 6 months ago
• riscv / riscv-smbios
  RISC-V SMBIOS Type 44 Spec
  ☆12Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• riscvarchive / riscv-clang
  ☆27Updated 5 years ago
• Minres / DBT-RISE-RISCV
  An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
  ☆35Updated 5 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 2 years ago
• openrisc / or1k-gcc
  GCC port for OpenRISC 1000
  ☆23Updated 3 years ago
• riscv-mcu / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC. Tweaked for microcontrollers.
  ☆29Updated 3 weeks ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆75Updated 5 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated 8 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆39Updated 7 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆64Updated 10 years ago
• lowRISC / rocket
  ☆31Updated 7 years ago
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago