NOP-Processor / NOP-SoC
System-on-chip design for NOP in NSCSCC 2023.
☆10Updated last year
Alternatives and similar repositories for NOP-SoC
Users that are interested in NOP-SoC are comparing it to the libraries listed below
Sorting:
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- ☆33Updated last month
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- The 'missing header' for Chisel☆20Updated last month
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆54Updated 9 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated this week
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆41Updated 9 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated this week
- ☆12Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆37Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Hardware design with Chisel☆32Updated 2 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Updated 2 years ago
- RISC-V 64 CPU☆10Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated last month
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Updated 5 years ago
- Platform Level Interrupt Controller☆40Updated last year
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆66Updated 9 months ago
- This is an IDE for YSYX_NPC debuging☆12Updated 5 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 6 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆67Updated 3 months ago