pulp-platform / axi_nodeLinks
AXI X-Bar
☆19Updated 5 years ago
Alternatives and similar repositories for axi_node
Users that are interested in axi_node are comparing it to the libraries listed below
Sorting:
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- ☆16Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆33Updated 2 months ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- ☆21Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆30Updated last month
- Implementation of the PCIe physical layer☆49Updated last month
- ☆14Updated 6 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆17Updated 3 weeks ago
- ☆20Updated 5 years ago
- AXI4 with a FIFO integrated with VIP☆21Updated last year
- Network on Chip for MPSoC☆26Updated 2 months ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Direct Access Memory for MPSoC☆13Updated 2 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆13Updated 8 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago