Alternatives and similar repositories for axi_spi_master

Users that are interested in axi_spi_master are comparing it to the libraries listed below

• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• pulp-platform / apb
  APB Logic
  ☆22Updated last month
• pulp-platform / apb_uart_sv
  ☆13Updated 6 years ago
• pulp-platform / axi_llc
  ☆33Updated last month
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆34Updated 7 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 6 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆34Updated 7 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• haifengch / axi_interconnect
  ☆28Updated 5 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆37Updated 8 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆35Updated 9 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆25Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated last week
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆35Updated 8 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆32Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆72Updated 6 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆53Updated last month
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago