☆26Oct 8, 2019Updated 7 years ago
Alternatives and similar repositories for axi_spi_master
Users that are interested in axi_spi_master are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆31Jun 13, 2021Updated 5 years ago
- ☆23Feb 22, 2020Updated 6 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- ☆39Oct 22, 2026Updated last week
- [UNRELEASED] FP div/sqrt unit for transprecision☆28Jul 27, 2026Updated 3 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆15Jul 5, 2019Updated 7 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆15Dec 19, 2025Updated 10 months ago
- ☆12Mar 24, 2023Updated 3 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- MATLAB-based FIR filter and profile designer☆10Jan 25, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simple single-port AXI memory interface☆51Jun 7, 2024Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- APB Logic☆29Sep 24, 2026Updated last month
- QSPI for SoC☆25Nov 8, 2019Updated 6 years ago
- ☆62Feb 18, 2019Updated 7 years ago
- General Purpose AXI Direct Memory Access☆83May 12, 2024Updated 2 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Jan 6, 2020Updated 6 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- ☆23Sep 23, 2015Updated 11 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 7 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- An Assortment of Convolutional Neural Networks☆11Mar 10, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Core protocol to AXI bridge☆11Sep 30, 2019Updated 7 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆153Jun 14, 2024Updated 2 years ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- ☆38Jun 3, 2024Updated 2 years ago
- Upstream eglibc + xilinx branches☆19Nov 7, 2013Updated 12 years ago
- Blockchain Offload Engine☆17May 5, 2018Updated 8 years ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆81Jun 22, 2020Updated 6 years ago