Alternatives and similar repositories for chisel-book

Users that are interested in chisel-book are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆33Updated 4 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆19Updated 2 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• scutdig / PyChip-py-hcl
  A Hardware Construct Language
  ☆43Updated 3 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• KireinaHoro / rocket-zynqmp
  ☆13Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• chipsalliance / espresso
  ☆40Updated last month
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆24Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆15Updated 6 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• ucb-bar / sha3
  ☆81Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 4 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 2 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆62Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆64Updated last year
• rhit-neuro / deca
  ☆22Updated 4 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago