Hardware design with Chisel
☆35Feb 9, 2023Updated 3 years ago
Alternatives and similar repositories for chisel-book
Users that are interested in chisel-book are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆607Aug 9, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Chisel Cheatsheet☆37Apr 13, 2023Updated 3 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Hardware Description Language Translator☆17Apr 20, 2026Updated last week
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- An almost empty chisel project as a starting point for hardware design☆36Jan 27, 2025Updated last year
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 7 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- ☆48Apr 16, 2026Updated 2 weeks ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 10 months ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- ☆22Nov 25, 2023Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Automatically exported from code.google.com/p/tpzsimul☆14Jul 7, 2015Updated 10 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 7 months ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆31Sep 17, 2025Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- coursier CLI launchers☆15Mar 12, 2026Updated last month
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- Rewrite XuanTieC910 with chisel3☆12Jul 1, 2022Updated 3 years ago
- Digital Design with Chisel☆910Apr 16, 2026Updated 2 weeks ago
- ☆22Oct 24, 2020Updated 5 years ago