redpanda3 / chisel-bookLinks
Hardware design with Chisel
☆34Updated 2 years ago
Alternatives and similar repositories for chisel-book
Users that are interested in chisel-book are comparing it to the libraries listed below
Sorting:
- ☆33Updated 5 months ago
- Chisel Cheatsheet☆33Updated 2 years ago
- A prototype GUI for chisel-development☆52Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- chipyard in mill :P☆78Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 3 months ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆29Updated 5 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆32Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆63Updated 3 years ago
- ☆81Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- Open-source high-performance non-blocking cache☆87Updated 3 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 6 years ago
- ☆31Updated 5 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- PCI Express controller model☆63Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- The 'missing header' for Chisel☆21Updated 5 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆60Updated last week
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- A Hardware Construct Language☆43Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago