Alternatives and similar repositories for tpzsimul

Users that are interested in tpzsimul are comparing it to the libraries listed below

• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 7 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆17Updated 4 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆41Updated 2 years ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated 11 months ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆75Updated 6 years ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆33Updated 5 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆11Updated 6 years ago
• gem5-hpca-2023 / gem5-tutorial-codespace
  ☆21Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• tukl-msd / DRAMSpec
  A High-Level DRAM Timing, Power and Area Exploration Tool
  ☆28Updated 4 years ago
• FCAS-LAB / Chiplet-Gem5-SharedMemory
  ☆31Updated last year
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆68Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated last month
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆26Updated 2 years ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆42Updated 7 years ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆48Updated 3 years ago
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆22Updated 6 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆55Updated 2 months ago
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆20Updated 9 years ago
• m-asiatici / MSHR-rich
  A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…
  ☆21Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated 2 months ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆72Updated last month
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆39Updated 6 years ago
• suchandler96 / gem5-NVDLA
  ☆31Updated 2 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆32Updated this week