Alternatives and similar repositories for pylibfst

Users that are interested in pylibfst are comparing it to the libraries listed below

• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• antmicro / verilator-verification-features-tests
  ☆23Updated this week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 8 months ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆39Updated 2 weeks ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆27Updated last week
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆46Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆14Updated last year
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆66Updated 6 months ago
• alexander-forster / cohdl
  A Python to VHDL compiler
  ☆16Updated last month
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 2 weeks ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• jkopanski / 802.15.4
  Medium Access Control layer of 802.15.4
  ☆12Updated 10 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆36Updated 2 weeks ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 2 months ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated 2 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago