huxuan0307 / XuanTieC910

Related projects: ⓘ

• chipsalliance / playground
  chipyard in mill :P
  ☆73Updated 10 months ago
• OSCPU / ysyxSoC
  ☆75Updated 2 weeks ago
• CherrySprings / CherrySprings
  ☆17Updated last year
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆36Updated 10 months ago
• lizhirui / DreamCore
  ☆61Updated last year
• OSCPU / oscpu-framework
  ☆43Updated this week
• sequencer / arithmetic
  ☆31Updated 7 months ago
• lingscale / cc01
  ☆31Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• OSCPU / chisel-playground
  ☆54Updated 2 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆57Updated 6 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆34Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆51Updated 8 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆61Updated 2 months ago
• sifive / block-inclusivecache-sifive
  ☆71Updated 2 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 5 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 3 months ago
• lizhirui / DreamCoreV2
  ☆19Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆63Updated this week
• OpenXiangShan / XS-Verilog-Library
  ☆35Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆44Updated 3 weeks ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆62Updated 4 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆46Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆111Updated last week
• chipsalliance / tilelink
  ☆23Updated 7 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆98Updated last year
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆11Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆18Updated 6 months ago
• OSCPU / yosys-sta
  ☆40Updated 2 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆40Updated this week