Alternatives and similar repositories for XuanTieC910:

Users that are interested in XuanTieC910 are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆78Updated 3 weeks ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 7 months ago
• OSCPU / chisel-playground
  ☆57Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 10 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• CherrySprings / CherrySprings
  ☆17Updated last year
• sequencer / arithmetic
  ☆32Updated 3 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆63Updated 5 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• RV-BOSC / OpenNoC
  ☆76Updated last week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆55Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 10 months ago
• yamak / axi-nodes
  ☆19Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆51Updated 2 weeks ago
• lizhirui / DreamCoreV2
  ☆21Updated last year
• lingscale / cc01
  ☆31Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• OSCPU / yosys-sta
  ☆49Updated 3 weeks ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated last month
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 2 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆39Updated 2 years ago
• chipsalliance / t1
  ☆128Updated this week