Alternatives and similar repositories for XuanTieC910

Users that are interested in XuanTieC910 are comparing it to the libraries listed below

• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆14Updated 4 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆43Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated 3 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• lingscale / cc01
  ☆31Updated 5 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆65Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• OSCPU / chisel-playground
  ☆67Updated 6 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated last week
• sequencer / arithmetic
  ☆33Updated 5 months ago
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆28Updated last week
• OSCPU / ysyxSoC
  ☆86Updated this week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆48Updated this week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆65Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• pulp-platform / redmule
  ☆73Updated last week
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• BriMonzZY / multi-mode-fft-processor
  R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
  ☆15Updated last month
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• wujun51227 / coffee-hdl
  coffeescript based hardware description language
  ☆14Updated 3 years ago