Verilog RTL Implementation of DNN
☆10Jun 26, 2018Updated 7 years ago
Alternatives and similar repositories for dnn-rtl
Users that are interested in dnn-rtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆19Nov 18, 2018Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆447Dec 2, 2019Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆19Oct 7, 2025Updated 5 months ago
- ☆10Dec 30, 2022Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- ☆43Mar 31, 2025Updated 11 months ago
- ☆15Jun 1, 2019Updated 6 years ago
- ☆25Feb 26, 2024Updated 2 years ago
- High Throughput Image Filters on FPGAs☆14Oct 17, 2017Updated 8 years ago
- Hardware design with Chisel☆35Feb 9, 2023Updated 3 years ago
- ☆17Nov 19, 2023Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Libraries useful for Dafny programs☆49Aug 19, 2025Updated 7 months ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Dec 10, 2018Updated 7 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆18May 4, 2023Updated 2 years ago
- Completed Verilog Pre-labs for the EECS2021 course at York University, Toronto, Canada☆11Mar 31, 2023Updated 2 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆28Jul 31, 2019Updated 6 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆60Sep 30, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Lock-free work stealing deque written in C. This is implemented after Chapter 16 of "The Art of Multiprocessor Programming."☆19May 27, 2011Updated 14 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- ☆25Aug 9, 2022Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- In this repository, Multidimensional Kalman Filter and sensor fusion are implemented to predict the trajectories for constant velocity mo…☆19Jun 30, 2022Updated 3 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆107Jan 17, 2026Updated 2 months ago
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆22Feb 3, 2026Updated last month
- 本项目是对《Neural Networks from Scratch in Python》读后的总结,在本项目中将应用Python(numpy)从0开始实现一个全连接神经网络,提供所有可运行代码,并对每一段代码加入注释(自己的理解)。本项目内容包括:全连接层、激活函数、损失…☆56Oct 7, 2023Updated 2 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- Python module for instrument control and automation.☆27Dec 5, 2024Updated last year
- Multiple 1-stencil implementations using nvidia cuda.☆12Dec 2, 2017Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Yet Another Simulation Architecture☆79Sep 17, 2020Updated 5 years ago