Csuk0914 / dnn-rtlLinks
Verilog RTL Implementation of DNN
☆10Updated 7 years ago
Alternatives and similar repositories for dnn-rtl
Users that are interested in dnn-rtl are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆33Updated last year
- ☆27Updated 5 years ago
- ☆13Updated 10 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 6 months ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- ☆18Updated last month
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 4 years ago
- ☆29Updated 5 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- course design☆22Updated 7 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last week
- Wraps the NVDLA project for Chipyard integration☆21Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆40Updated 8 months ago
- ☆34Updated 5 months ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆17Updated 3 weeks ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆30Updated 2 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆25Updated 2 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago