Csuk0914 / dnn-rtlLinks
Verilog RTL Implementation of DNN
☆10Updated 7 years ago
Alternatives and similar repositories for dnn-rtl
Users that are interested in dnn-rtl are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- ☆27Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 12 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- ☆13Updated 10 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 4 months ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- course design☆22Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- ☆15Updated last week
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 6 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- The official NaplesPU hardware code repository☆17Updated 5 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆27Updated 7 years ago
- ☆31Updated 3 months ago
- ☆29Updated 4 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆26Updated 3 weeks ago
- verification of simple axi-based cache☆18Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- CNN accelerator☆27Updated 8 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 3 months ago